Contrastive learning operates on a simple yet effective principle: Embeddings of positive pairs are pulled together, while those of negative pairs are pushed apart. In this paper, we propose a unified framework for understanding contrastive learning through the lens of cosine similarity, and present two key theoretical insights derived from this framework. First, in full-batch settings, we show that perfect alignment of positive pairs is unattainable when negative-pair similarities fall below a threshold, and this misalignment can be mitigated by incorporating within-view negative pairs into the objective. Second, in mini-batch settings, smaller batch sizes induce stronger separation among negative pairs in the embedding space, i.e., higher variance in their similarities, which in turn degrades the quality of learned representations compared to full-batch settings. To address this, we propose an auxiliary loss that reduces the variance of negative-pair similarities in mini-batch settings. Empirical results show that incorporating the proposed loss improves performance in small-batch settings.

Physically unclonable function (PUF) is a lightweight encryption technique that generates random digital keys (responses) using intrinsic process variations of devices, which is a promising solution for Internet of Things (IoT) security due to its compatibility with constrained resources. Recent attempts to adopt nonvolatile memory (NVM) into PUFs have enhanced stability through a write-back technique that maintains consistent responses from the enrollment phase even under wide environmental variations by storing the response in the NVM device. However, the stability of the previous NVM PUFs is limited by the low on/off ratio of the NVMs. In addition, the circuit required to implement the write-back technique poses challenges of increased area and energy consumption. Considering the hardware limitations and power constraints of IoT devices, this paper proposes a ferroelectric field-effect transistor (FeFET) PUF as a suitable security solution. The high on/off ratio of FeFET and the proposed auto write-back technique that does not require additional circuitry realize the stability improvement (a bit error rate of <0.0001%) under wide environmental variations without incurring area and energy overheads. The negligible off current of FeFET prevents static power consumption, which leads to the lowest energy consumption of 6.70e-15 J during the response generation of the FeFET PUF. In addition, the compact PUF cell composed of two FeFETs achieves a high density of 87.37 F2.

Nonvolatile processors (NVPs) are promising for energy-constrained internet-of-things applications in which frequent switch to standby mode occurs due to their fast and energy-efficient backup and restore operations of locally embedded nonvolatile flip-flops (NV-FFs) with zero leakage current. In addition, the most effective method to reduce dynamic energy consumption is to lower the supply voltage (${V} _{DD}$). The sense-amplifier-based flip-flop (SAFF) is considered a suitable choice for the low${V} _{DD}$operation, since it does not suffer from setup time degradation as${V} _{DD}$lowers. This study presents two ferroelectric FET (FeFET) nonvolatile SAFFs (FeFET NV-SAFF-1 and -2) that exhibit significantly low sequencing overhead (setup time + clock-to-Q time) at low${V} _{DD}$and consume low operating energy in the range of femto joules with compact layout area. The FeFET NV-SAFF-1 can operate robustly at low${V} _{DD}$even with a low resistance ratio. The FeFET NV-SAFF-2 has no area overhead and achieves the best power-performance-area at low${V} _{DD}$among state-of-the-art and proposed FeFET NV-FFs.

Fast communication between networking devices increases the importance of the ternary content addressable memory (TCAM). The demands for low energy in networking devices have accelerated the research on nonvolatile TCAMs that store data without the power supply. Recently, ferroelectric field-effect transistors (FeFETs), nonvolatile three-terminal devices with a high on/off ratio, have been adopted for TCAMs. Although the previous FeFET TCAMs consume low write energy with a significantly compact TCAM cell area, they suffer from write problems: 1) the write scheme cannot afford the saturated polarization switching in FeFETs and 2) the states stored in the unselected TCAM cells are changed during the write operation. In addition, search yield is deteriorated by wide process variations of FeFETs. This paper proposes a novel FeFET TCAM that is free from the write problems of the previous FeFET TCAMs and tolerant to process variations. This paper also proposes a novel match line scheme to improve search energy and time by reducing match line capacitance and the amount of discharged voltage in the match evaluation phase. Industrial-compatible 28 nm technology-based simulation results with the Preisach FeFET model show that the proposed FeFET TCAM achieves the highest search yield.

Recently, with the increase in popularity of Internet of Things (IoT) devices, cryptographic protection techniques have become necessary for high-security applications. In general, IoT devices have strict power and area constraints. Thus, use of a physical unclonable function (PUF), which can generate a secret key at low cost, can be advantageous for high-security IoT devices. This paper presents a novel environmental-variation-tolerant (EVT) magnetic tunnel junction (MTJ)-based PUF that has a small area, high randomness, and low bit error rate (BER) compared to previous PUFs. The simulation results obtained using industry-compatible 65-nm model parameters indicate that the proposed PUF exhibits an inter-chip Hamming distance of 0.4901 and entropy of 0.9997, which proves the randomness of the PUF response. In addition, the proposed PUF exhibits the lowest BER across a wide voltage range (0.9 V-1.3 V) and temperature range (-25 °C - 75 °C) compared with previous PUFs.

In physically unclonable functions (PUFs), generating random cryptographs is required to secure private information. Various memory-based PUFs (MemPUFs), where cryptographs are generated independently from each PUF cell to increase the unpredictability of the cryptographs, have been proposed. Among them, the spin-transfer torque magnetic random-access memory MemPUF generates constant responses under temperature and voltage variations by exploiting a magnetic tunnel junction (MTJ) as the variation source. However, its response stability is diminished by the different characteristics of the two access transistors used in a PUF cell. To solve this problem, a novel PUF array that employs a diode-connected transistor and a shared access transistor, is proposed. In addition, a two-step postprocessing is adopted: 1) a write-back technique that amplifies the initial mismatch of MTJ resistances, and 2) a cell-classification technique that detects unstable PUF cells and discards their responses. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm technology show that the proposed PUF system achieves the highest independence (autocorrelation factor of 0.0306) and the lowest maximum bit error rate (BER) under temperature and supply-voltage variations (<; 0.01% and 0.04% in the ranges of -25 to 75 °C and 0.8-1.2 V, respectively) compared with conventional PUF systems that exploit independent variation sources.