Chiplet-based systems provide a scalable platform for heterogeneous integration, but permanent faults in interconnects and memory cells challenge their reliability. While standards like Universal Chiplet Interconnect Express (UCIe) employ single-domain system Error Correction Code (ECC) simplify architecture, they often limit fault isolation and recovery. This paper proposes a dual-mode Online Built-In Self-Repair (OBISR) architecture for unified detection and repair of both interconnect and memory faults during post-bond testing and in-field operation. Unlike conventional methods that merely expand ECC capacity, the OBISR targets the root causes of persistent errors by repurposing existing Content-Addressable Memory (CAM) and pathfinding logic. A hierarchical CAM structure classifies faults using spatial and recurrence patterns of ECC metadata to distinguish permanent defects from transients. Memory faults are masked via logical redirection, while interconnect faults are rerouted, both operating outside the datapath to ensure zero performance degradation. Evaluations demonstrate that the OBISR improves system-level resilience by 235.49% and reduces hardware area by 16.69% compared to conventional schemes. Its integrated dual-domain and dual-mode capabilities offer a robust, scalable solution for next-generation chiplet reliability.

In dynamic random-access memory (DRAM), memory redundancy analysis (RA) is a crucial process for enhancing memory yield and reducing production costs. It finds a memory repair solution by efficiently allocating the limited number of spare cell lines that replace a faulty cell. However, it is challenging to quickly find a memory repair solution because RA is an NP-complete problem. To address this issue more effectively, we present a powerful early termination-based high-speed RA method. This method rapidly assesses memory repairability, terminating the RA process early in cases where repair is impossible, or a solution can be easily found. Additionally, by dividing faulty cells into several groups, the proposed RA method finds fast and approximate albeit nonoptimal solution sets for each group. This facilitates the rapid acquisition of a memory repair solution without the need to search for all the optimal solution sets. These features enable RA to be promptly executed while ensuring the repair solution for any repairable memory. Experimental results demonstrate that the proposed RA method can find a repair solution faster than the existing RA methods.

A voltage-divider-based through-silicon-via (TSV) test architecture tests the TSV by using the voltage value differently divided according to TSV defects. This architecture is widely used for TSV testing owing to its small hardware overhead and high test speed. However, the existing voltage-divider-based TSV test architectures are vulnerable to process–voltage–temperature (PVT) variations and noise. In addition, they cannot effectively detect pinhole defects. This study proposes a novel error-tolerant voltage-divider-based TSV test architecture to address these problems. The proposed architecture reduces the test errors by appropriately adjusting the on-resistance value of each MOSFET and adding a compensator circuit. In addition, it effectively detects the pinhole defects by modifying the voltage divider structure and changing the MOSFET control method. Experimental results reveal that the proposed architecture promptly tests various TSV defects and significantly reduces the test errors.

High-bandwidth memory (HBM) is the latest 3-D-stacked dynamic random access memory (DRAM) standard adopted in Joint Electron Device Engineering Council (JEDEC). It has many advantages, such as high bandwidth, large capacity, and low power consumption, but mass production is challenging due to its low yield and reliability. One of the reasons is that through-silicon-vias (TSVs) are prone to defects. Therefore, HBM requires a TSV built-in self-repair (TBISR) architecture that can repair the TSV at a high repair rate even after chip shipment; however, implementing it through existing TSV repair architectures is difficult. They have a large area overhead or a low repair rate. In addition, they lack consideration for bidirectional TSV repair. To address these issues, this article proposes a novel TBISR architecture that can repair bidirectional TSVs and has a small area overhead and a high repair rate. Experimental results show that the proposed architecture, capable of bidirectional TSV repair, has a high repair rate, despite the small size compared to other architectures.

Built-off self-test (BOST) is a widely used technique to reduce the test cost. It makes it possible to test high-speed dynamic random-access memory (DRAM) without using a costly high-performance automatic test equipment (ATE). However, the currently used BOSTs require many ATE connection pins, which degrade the cost reduction effect. In this article, we propose a novel reduced-pin-count BOST to reduce the test cost. The proposed BOST uses bidirectional pins to employ the pins as efficiently as possible. Thus, even if the same amount of data is transferred, fewer pins are required than the previous BOSTs. In addition, it reduces the amount of output data by sending only the information necessary for a DRAM repair process. This is possible because the DRAM repair process requires only the location information of some faulty cells. Therefore, the proposed BOST can send output data with fewer pins compared with the previous BOSTs. Experimental results indicate that the proposed BOST can test high-speed DRAMs using a few ATE connection pins.

Invasive attacks, such as microprobing or focused-ion-beam (FIB) circuit editing are serious threats to security-related semiconductors. To ensure that there is security against invasive attacks, an effective countermeasure is to use a protective layer as a secure shield. Previous secure shield methods can be classified into one of two categories; detection circuits based on the delay difference or block ciphers. For the former, timing asymmetries caused by the capacitance of the probe are detected. The main drawback of this method is that it is highly vulnerable to chip editing by FIB equipment. FIB circuit editing can easily cripple the detection circuits of the secure shield. In contrast, the cryptographically secure shield based on the block cipher can provide strong protection against FIB circuit editing. However, it is prone to microprobing attacks because of its inability to detect the capacitance load of the probe. In this article, we propose a robust secure shield architecture against invasive attacks, including both probe attempts and the FIB circuit editing. The proposed method is based on the detection circuits with low hardware overhead and fast-analysis time and includes protection circuits to prevent information from being leaked.