To reduce power consumption associated with data transmission and monitoring in next-generation wireless body sensor networks (WSBNs), compressive sensing (CS), a signal-processing technique for signal reconstruction from a limited number of measurements, was proposed. In CS, knowledge of the signal sparsity under some basis is used to cast the reconstruction problem as the solution of an ℓ1-penalized underdetermined linear system, a data-intensive task in energy-hungry conventional digital solvers. By eliminating the energy and latency overheads associated with continuous data shuttling between the memory and processing units, in-memory computing (IMC) may be a key enabler for highly energy-efficient next-generation WSBNs.Here, we show a novel closed-loop IMC (CL-IMC) circuit for signal reconstruction in the CS framework exploiting nonlinearities of analog operational amplifiers. We derive closed-form equations to describe the circuit operation and characterize its solution time and accuracy. We benchmark the circuit performance in electrocardiogram signal reconstruction against a floating-point 64-bit (FP64) digital solver, obtaining up to 1120 × energy consumption reduction. These results support the position of CL-IMC as a promising candidate for energy-efficient data processing in edge devices for biometric applications.

Wireless communication systems are the backbone of today's digital society. To achieve unprecedented throughput and efficiency, 5G and 6G networks will leverage parallel communication over multiple spatial channels under the massive MIMO (multiple-input multiple-output) framework. One of the main limitations of MIMO is its heavy load of matrix operations, a task for which von Neumann-based computers are deeply unoptimized. This bottleneck can be solved by in-memory computing (IMC), where computation is performed directly within the memory, thus eliminating the constant data shuttling between the memory and the processing unit. Here, we provide an experimental validation of a closed-loop IMC (CL-IMC) system on a 90 nm CMOS integrated circuit. Zero-forcing and regularized-zero-forcing decoding are executed with$14\times 7$MIMO link. The hardware demonstration shows 99.91% accuracy, which is close to a floating-point precision decoder. These results support CL-IMC as a promising candidate for data processing in massive MIMO for next-generation cellular networks.

In-memory computing (IMC) is gaining momentum as the most promising candidate for the upcoming non-von-Neumann, machine learning-optimized computing paradigm. Its intrinsic parallelism is well-suited to accelerate matrix-vector multiplications (MVM), which prove challenging for traditional architectures and are a fundamental operation in principal component analysis (PCA), one of the most renowned algorithms for data classification. Here, we show an experimental demonstration of a novel, IMC-based PCA algorithm by in-memory power iteration and deflation executed in a 4-kbit array of resistive random-access memory (RRAM). Our algorithm achieves 95.25% classification accuracy on the Wisconsin Diagnostic Breast Cancer dataset, matching closely results of a floating-point machine while providing a $250\times$ improvement in energy efficiency.

The increasing demand for data-intensive computing applications, such as artificial intelligence (AI) and more specifically machine learning (ML), raises the need for novel computing hardware architectures capable of massive parallelism in performing core algebraic operations. Among the new paradigms, in-memory computing (IMC) with analogue devices is attracting significant interest for its large-scale integration potential, together with unrivaled speed and energy performance. Here, we present a fully-analogue, universal primitive capable of executing linear algebra operations such as regression, generalized least-square minimization and linear system solution with and without preconditioning. We study the impact of the main circuit parameters on accuracy and bandwidth with analytical closed-form expressions and SPICE simulations. Scaling challenges due to parasitic resistance/capacitance and their impact on key parameters such as bandwidth and accuracy are discussed. Finally, a comparison with existing solvers belonging to the same IMC framework is made to assess advantages and disadvantages of the proposed circuit.

Neuronal activity of recurrent neural networks (RNNs) experimentally observed in the hippocampus is widely believed to play a key role for mammalian ability to associate concepts and make decisions. For this reason, RNNs have rapidly gained strong interest as computational enabler of brain-inspired cognitive functions in hardware. From the technology viewpoint, nonvolatile memory devices such as phase change memory (PCM) and resistive switching memory (RRAM) have become a key asset to allow for high synaptic density and biorealistic cognitive functionality. In this work, we demonstrate for the first time associative learning and decision making in a hardware Hopfield RNN with 6 spiking neurons and PCM synapses via storage, recall and competition of attractor states. We also experimentally demonstrate the solution of a constraint satisfaction problem (CSP) namely a Sudoku with size 2×2 in hardware and 9×9 in simulation. These results support spiking RNNs with PCM devices for the implementation of decision making capabilities in hardware neuromorphic systems.