Federated Learning (FL) has emerged as a promising privacy-preserving collaborative model training paradigm without sharing raw data. However, recent studies have revealed that private information can still be leaked through shared gradient information and attacked by Gradient Inversion Attacks (GIA). While many GIA methods have been proposed, a detailed analysis, evaluation, and summary of these methods are still lacking. Although various survey papers summarize existing privacy attacks in FL, few studies have conducted extensive experiments to unveil the effectiveness of GIA and their associated limiting factors in this context. To fill this gap, we first undertake a systematic review of GIA and categorize existing methods into three types, i.e., optimization-based GIA (OP-GIA), generation-based GIA (GEN-GIA), and analytics-based GIA (ANA-GIA). Then, we comprehensively analyze and evaluate the three types of GIA in FL, providing insights into the factors that influence their performance, practicality, and potential threats. Our findings indicate that OP-GIA is the most practical attack setting despite its unsatisfactory performance, while GEN-GIA has many dependencies and ANA-GIA is easily detectable, making them both impractical. Finally, we offer a three-stage defense pipeline to users when designing FL frameworks and protocols for better privacy protection and share some future research directions from the perspectives of attackers and defenders that we believe should be pursued. We hope that our study can help researchers design more robust FL frameworks to defend against these attacks.

Federated learning (FL) is a powerful technology that enables collaborative training of machine learning models without sharing private data among clients. The fundamental challenge in FL lies in learning over extremely hetero-geneous data distributions, device capacities, and device state availabilities, all of which adversely impact performance and communication efficiency. While data hetero-geneity has been well-studied in the literature, this paper introduces FLHetBench, the first FL benchmark targeted toward understanding device and state heterogeneity. FL-HetBench comprises two new sampling methods to generate real-world device and state databases with varying het-erogeneity and new metrics for quantifying the success of FL methods under these real-world constraints. Using FL-HetBench, we conduct a comprehensive evaluation of existing methods and find that they struggle under these settings, which inspires us to propose BiasPrompt+, a new method employing staleness-aware aggregation and fast weights to tackle these new heterogeneity challenges. Experiments on various FL tasks and datasets validate the effectiveness of our BiasPrompt+ method and highlight the value of FLHet-Bench in fostering the development of more efficient and robust FL solutions under real-world device and state constraints.

The emergence of mixed-precision quantization (MPQ) applied to edge AI models highlights the critical need for hardware support. It is a promising model compression approach with minimal accuracy loss but poses a notable hardware design challenge in the intricate balance required between computing reconfigurability and the resulting area or energy overheads. As the Compute-in-Memory (CiM) paradigm becomes prevalent for accelerating edge inference and demonstrates promising results in enhancing energy efficiency by eliminating overloaded data traffic, efficient in-memory computing circuitry becomes paramount to maximize these advantages. While the memory cell itself cannot handle complex arithmetic logic, especially in the context of MPQ-supporting mult-precision computing, the peripheral pairing module is required to be modular, portable, and scalable. In this paper, we propose a novel bit-precision configurable arithmetic module based on binary segmentation, supporting fine-grained precision ranging from 2 to 8 bits. This module achieves a peak throughput of 16 GOPS and maximum energy efficiency of 8.56 TOPS/W, occupying only 1778 μm2in 28nm technology node. The throughput and energy efficiency achieve 1.18x and 6.58x improvements compared with baseline work. Its portability enables seamless integration with various memory technologies, enhancing support for MPQ efficiently.