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Xianjun Ge

dblp:265/0797 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 50% Reconfigurable computing and FPGAs · 50%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA-based heterogeneous computing
CPU-FPGA platform
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020
Reconfigurable computing and FPGAs
FPGA accelerator
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA-based key-value store
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020
Storage systems › key-value storage
in-memory key-value store
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020
Storage systems
key-value storage
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020
Storage systems › key-value storage
RDMA-based key-value store
0.412020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA · IEEE Trans. Parallel Distributed Syst. 2020

Methods — techniques the papers use, named apart from their topics

hardware acceleration · 0.4RDMA · 0.4
YearPublicationVenuePosition
2020 FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA
abstract
In-memory key-value store (IMKVS) has gained great popularity in data centers. However, big data brings great challenges in performance and power consumption because of the general-purpose Von Neumann computer architecture. Remote direct memory access (RDMA) technology supporting zero-copy networking could partly alleviate the problem but is still not efficient for KVS. To overcome this problem, we present a flexible and ultra-low-latency IMKVS system named FULL-KV, based on a CPU-FPGA heterogeneous architecture. The FPGA serves as a KVS accelerator that can bypass the CPU and implement both the network stacks and the KVS processing with a highly parallel hardware architecture. The system latency of FULL-KV can achieve as low as 1.5μs/2.2μs for the PUT/GET operation, which is 3.0x/1.5x faster than current state-of-the-art hardware-based KVS systems. Besides, FULL-KV can support 4x larger values (up to 4M bytes). Given a total Ethernet bandwidth of 20Gbps, the peak throughput of the single-node FULL-KV can reach 26.0 million key-value operations per second (Mops). In the two-node test system with a commercial Ethernet switch, the peak throughput can reach 52Mops, manifesting the system scalability and practicability.
Yunhui Qiu, Jinyu Xie, Hankun Lv, Wenbo Yin, Wai-Shing Luk, Lingli Wang, Bowei Yu, Xianjun Ge, Zhijian Liao, Xiaozhong Shi
IEEE Trans. Parallel Distributed Syst.9