This paper presents the architecture and implementation of a low-noise sub-sampling phase-locked loop (SSPLL) for mm-wave frequencies. It leverages an LC oscillator with a novel resonator, a digital lock assist and frequency calibration system as well as a novel charge pump implementation. The charge pump eliminates the pulser and runs continuously, which significantly reduces its power consumption while maintaining equal noise performance. The calibration system solves the lock problem of the SSPLL by implementing a lock/frequency search to prevent non- and false-lock. The LC oscillator employs an optimized resonator which combines both the inductor and the capacitor on the same metal, resulting in a very high quality factor by eliminating the interconnect resistance within the resonator. The SSPLL was implemented and simulated in a 22-nm-FDSOI technology, alongside with measurement results of the LC oscillator, which was fabricated in the same technology.

This paper presents an 11-bit 12GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30fs step-size. The ADC achieves a voltage gain of 8.55dB in steering direction. An overall SFDR and SNDR above 68dBc and 55dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.

In this paper, a novel charge pump for sub-sampling phase-locked loops (SSPLLs) is presented. Contrary to the conventional charge pump, the proposed implementation eliminates the previously-required pulser. This is achieved by using all sample data from the ping-pong sub-sampling phase detector as opposed to only every second point, which enables the charge pump to run pseudo-continuous. This virtually raises the reference frequency by a factor of two, which is beneficial for the phase noise performance of the phase-locked loop while fulfilling the requirements for bandwidth of reference buffers, switches etc. Furthermore, eliminating the pulser enables a highly power-efficient charge pump design, leveraging higher SSPLL FoM. The proposed charge pump is implemented in a 22-nm fully-depleted silicon-on-insulator technology. The power and area consumption are reduced by roughly 80% and 55%, with similar effective gain, noise and offset performance to the conventional design.

Next-generation data centers demand higher bandwidth, generating interest in 224 Gbit/s wireline transceivers. This paper analyzes the performance of PAM-4/PAM-6/PAM-8 for a co-packaged optical link including different channel lengths at 224 Gbit/s with all transceiver blocks, DSP equalization, and NEXT/FEXT crosstalk. With a 32-tap FFE and 1-tap MLSE equalization, a SER−3is achievable for PAM-4/PAM-6 for a channel attenuation <13dB at 56 GHz. Furthermore, a detailed power analysis is done for the modulations including all relevant transceiver blocks.

This paper presents a 56 GHz Sub-Sampling Phase-Locked Loop (SSPLL) for an optical transceiver system. It employs an LC oscillator without frequency multiplier featuring a novel combined resonator for high purity signals, a differential track-and-hold with dummy samplers, a charge pump with feedback amplifiers and specialized input pairs for high voltage operation. The sub-sampling architecture allows for ultra-low phase noise at low offset frequencies, while far-out phase noise is minimized due to the used high-purity oscillator. The phase noise at an 1MHz amounts to - 127dBc/Hz, resulting in a total integrated jitter of 19 fs (range from 1 kHz to 1 GHz). This 56 GHz SSPLL enables next-generation wire-line optical communication standards with over 100Gbit/s.