This paper proposes a 1.5 GS/s 9-bit two-stage pipelined SAR analog-to-digital converter (ADC) in 28 nm CMOS. Simultaneously with amplification, the inter-stage residue is converted to time-domain (TD) and quantized by a TDC. This results in significant resolution improvement of the second stage under the speed of 1.5 GS/s. A double-edge quantized TDC with improved time resolution is proposed for higher conversion speed in the time domain and less power consumption. Moreover, a cascode switching inverter-based open-loop amplifier is proposed featuring low gain error, fast settling, and low power. With a sampling speed of 1.5 GS/s, the simulation results show that the ADC achieves 55 dB SNDR and 66.7 dB SFDR at the Nyquist frequency and 1-Vppinput swing, while the power consumption is 6.86 mW, yielding a Walden FoM of 10.2 fJ/con-step.

This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit voltage-domain stage with a 6-bit time-domain (TD) backend to take full advantage of the voltage and time domains. A high-speed hybrid-loop residue amplifier (RA) is proposed with a settling time of less than 150 ps, while a non-symmetrical pipeline timing utilizing a 25% duty cycle clock is used to increase the TD quantization time and the settling time margin of the RA. A low-power and small-area gated-ring-oscillator-based TD backend is employed, which operates at 4-GS/s with 6-bit resolution. The prototype hybrid ADC occupies an active area of 0.0114 mm2. Under a 1-V power supply and Nyquist input, the chip achieves a measured ENOB of 6.46 bits at a conversion rate of 4 GS/s, while the power consumption is 10.6 mW and the FoMw is 29.9 fJ/conversion-step.

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm2active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm2active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is$3.6~\mu \text{s}$) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications.

In this brief, a fully digitized pulse generator with programmable pulse number and width is used as an ultrawideband (UWB) pulse transmitter with 17.7-dBm output power for see-through-wall (STW) radar. A fully differential operation broadband CMOS power amplifier (PA) with a power-switchable mode and fast settling time for pulse radar is presented, achieving excellent power consumption, considerable output power, and a -3-dB bandwidth from 3.6 to 6.6 GHz. The on-chip transformer is used for impedance transformation in the output and converting signals from the differential to single ended. Fabricated in a 65-nm standard CMOS process, the operating carrier frequency range of the transmitter covers 3.2-5.8 GHz and the pulsewidth can be adjusted from 0.75 to 1.2 ns. The number of pulses varies from 4 to 1. At 10-MHz pulse repetition frequency (PRF), the maximum peak-to-peak voltage of the transmitter output pulse reaches 3.8 V with 50-Ω load, and the corresponding pulsewidth is 0.75 ns. The equivalent power is 17.7-dBm after calibration, and the average power consumption is only 22.5 mW.