In the age of artificial intelligence, large language models (LLM) require rapid development along with massive volumes of training data and parameter storage. Over the past decade, 3D NAND flash memory has emerged as the dominant non-volatile memory technology due to its high bit density and large capacity. However, because of its 3D vertical stacking technique and array designs, 3D NAND flash memory has more complicated data loss mechanisms compared to 2D NAND flash memory. As bit densities rise to Quad-level-cells (QLC), the small read margins will further complicate and make the situation more unpredictable. In this work, we propose an error-bit prediction model in this paper for 3D QLC NAND flash memory with the charge-trap (CT) cell structure based on a thorough analysis of multiple parameters that affect the error-bit distributions, including read disturb (RD) and degradation from program/erase (PE) cycles. Specifically, we develop the whole-block prediction (WBP) and the dynamic-worst-page prediction (DWPM) models. It is shown that the proposed models can be used for high-precision error-bit prediction to guarantee data reliability in commonly used NAND-based storage systems based on the characterization results of raw NAND chips.

Three-dimensional (3D) NAND flash memory has become quite popular and is now widely used in data centers and mobile devices due to its outstanding storage density and cost-effectiveness. Larger storage capacity is made possible by 3D quad-level cell (QLC) NAND flash memory with the charge-trap (CT) structure, which stores four bits in each cell. However, data reliability is sacrificed in exchange for greater capacity. The lifespan of data retention is crucial for non-volatile storage. Thus, an important role is played by the Arrhenius model, which is widely used for lifespan prediction and high-temperature acceleration testing. Interestingly, we discover that the conventional Arrhenius model is inaccurate after analyzing the data retention properties of 3D QLC NAND flash memory. An empirical model is proposed for changing the apparent activation energy (Ea) based on the influence of different parameters, in order to accurately predict data lifespan and perform accelerated experiments. This developed model provides a temperature-and cycle-related parameter table for Ea, which is useful for high-temperature acceleration testing examinations. Simultaneously, we observe a linear connection between the 40∘C data retention time mapping and the other temperatures. We evaluate the effects of the modified Ea model and the classic Arrhenius model with the epitaxial data and conclude that the former can reduce the error by approximately 70% to a maximum.

Solving partial differential equations (PDEs) requires precise numerical iterations that impose significant demands on computational resources and memory capacities, which can be addressed by adopting computing-in-memory (CIM) architecture to reduce the latency and power consumption during data transmission. Among PDEs, nonlinear PDEs present heightened complexities in both analytical investigations and numerical simulations as the presence of nonlinear terms introduces intricate dynamics and mathematical intricacies. The high-precision requirements of PDE solvers, particularly for nonlinear PDE solvers, pose challenges in constructing CIM PDE solvers. In this work, a flash-based high-precision PDE solver has been demonstrated to solve the intractable nonlinear partial differential equation. It’s based on 55nm NOR flash technology with well-optimized Program/Erase (PE) schemes. Utilizing the proposed optimization scheme, the PE endurance can be largely enhanced up to$10^{10}$cycles, which is a record high with suppressed cell degradation and robust reliabilities. Then, applying the Fourier neural operator (FNO) to the optimized flash-based high-precision CIM (32-bit) in the hardware system, a series of nonlinear PDEs can be solved with ~2TOPS/W high energy efficiency, which is$\sim 110\times $higher than CPU. Our optimization strategies make it feasible to use flash-based CIM for high-precision computing with frequent weight updating and the demonstrated PDE solver provides an energy-saving solution to implement general-purpose computation tasks.

3-D NAND flash memory is the ubiquitous nonvolatile memory (NVM) on the market because of its large storage capacities, high reliability, and low bit cost. The reliability characteristics of 3-D NAND flash memory, however, are considerably different from those of 2-D NAND flash memory due to the peculiar architectures. In this article, read disturb (RD) at various program/erase (P/E) stages is thoroughly explored. To adjust the low-density parity check (LDPC) codes dynamically and extend the lifetime of 3-D NAND flash memory, short-term lifetime prediction models of RD and endurance are proposed based on in-depth studies on the correlations of fail bit count (FBC) at various lifetime stages, and their accuracy is tested experimentally. A new short-term warning system (STWS) is proposed to extend the lifetime of 3-D NAND-based storages. It consists of the error-bits’ prediction module (EBPM) and the self-adjustable LDPC codes module (SLDPC), where EBPM predicts FBC periodically and SLDPC preallocates LDPC codes for future use based on the result of EBPM. The experimental result shows that our prediction models have high reliability, and STWS can effectively prolong the lifetime of NAND flash. The findings of this study provide fundamental insights into FBC degradation in 3-D NAND flash, as well as a simple and practical method for building 3-D NAND-based storage with high reliability.

In this paper, read disturb (RD) at various program/erase (P/E) stages has been thoroughly explored, and short-term lifetime prediction models of RD and endurance are proposed. Based on these, a new short-term warning system (STWS) is proposed, which can extend the lifetime of 3D NAND-based storage by adjusting LDPC codes dynamically. The experimental result shows that the proposed prediction models have high reliabilities, and STWS can effectively prolong the lifetime of NAND flash.

3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively.

3-D NAND flash memory has been attracting much attention owing to its ultrahigh storage density and low bit cost, and it has been widely applied in data centers and mobiles. 3-D triple-level-cell (TLC) NAND flash memory can achieve much larger storage capacity by storing 3 bits in each cell. However, the data reliability issues induced by data retention (DR) and read disturb (RD) greatly limit 3-D TLC NAND applications in hot data storage where the stored data are frequently accessed and RD is more serious. In this article, we first systematically study the retention correlated RD (RCRD) errors in 3-D charge trap (CT) TLC NAND flash memory under various conditions. Error characteristics and underlying mechanisms much different from 2-D NAND flash memory are observed: 1) for RCRD with short retention-after data program, error bits increase due to the negative-shift of program states and 2) for RCRD with long retention-after retention 12 h, error bits can be partially recovered on the contrary due to the charge compensation. We propose schemes of precharge the storage layer (PCSL) and thermally stabilize the storage layer (TSSL) to improve the reliability of 3-D NAND flash memory. By using these two methods, experimental results show that raw bit error rates (RBERs) can be significantly reduced by 30% and 20%, respectively.