Non-binary low-density parity-check (NB-LDPC) codes are a prominent class of error-correction codes, offering superior error-correcting performance compared to their binary counterparts. However, previous NB-LDPC decoders suffer from high processing complexity and significant memory overhead when supporting high-order Galois fields and long codeword lengths. To address these challenges, the proposed decoder leverages the trellis min-max algorithm and adopts a column-layered decoding schedule with on-the-fly message computation to reduce memory requirements. Additionally, the proposed column-layered algorithm shares up-to-date information among columns, enhancing the convergence speed of the baseline design. Considering the structure of high-rate NB-LDPC codes, we introduce multi-column processing with an optimized banked memory architecture while minimizing parallel processing overhead through submodule optimization. Fabricated using a 28-nm CMOS technology, the prototype 4KB 0.9-rate decoder achieves a 1.42-fold improvement in area efficiency compared to state-of-the-art designs. While the proposed design is motivated by the requirements of storage applications, its modular organization and scalable parallelism also allow adaptation to diverse domains such as wireless and optical communications.

The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization.

Due to an iterative nature, a low-density parity-check (LDPC) decoder is associated with a long latency, being a major bottleneck of the baseband processor in wireless communication systems. Based on the practical min-sum (MS) decoding method, in this paper, we present a cost-effective algorithm for reducing the processing latency of LDPC decoders. By checking the number of short-length cycles in the LDPC code structure, the proposed method dynamically changes the reweighting factor at the iterative operations, successfully reducing the average number of iterations. In addition, we present several optimization schemes to mitigate the hardware overheads resulting from the proposed reweighting scheme. In a 65-nm CMOS process, a prototype IEEE 802.11ay LDPC decoder optimized by the proposed schemes reduces the decoding latency by 1.7 times with negligible overheads compared with the contemporary designs.