Despite the maturity of Multi-bit Flip-Flops (MBFF) clustering in modern Electronic Design Automation (EDA) tools for saving power, there remains a trade-off between the flexibility to cluster flip-flops and the overall quality of results (QoR). This paper proposes a novel approach to MBFF clustering, integrating early-stage physical and timing awareness to optimize the design quality. Our pre-placement MBFF clustering algorithm addresses this trade-off by incorporating early distance estimation and predicted skews, improving timing conditions without compromising power savings. We evaluate our approach using widely-used benchmark circuits, demonstrating significant improvements in power savings and timing compared to state-of-the-art techniques. Notably, our method achieves an average improvement of 22.5% in Worst Negative Slack (WNS) and 33.91% in Total Negative Slack (TNS), while reducing power by 3.01% compared to commercial tools with MBFF clustering enabled at placement. Against the state-of-the-art pre-placement MBFF clustering algorithm, our methodology shows 25.59% and 37.97% improvements in WNS and TNS, respectively, while further reducing power by 3.08%. In addition, the proposed approach proves robust against variations in early-stage path delay estimation, maintaining superior performance even with deviations of over 20%.

Digital twin (DT) is a promising technology for responding to Industry 4.0 and realizing comprehensive automation and virtualization. In the Web3.0-powered 5G/6G era, the expansion of the industrial data and closer interaction among cross-industrial entities pose new security challenges for DT industrial systems. As a prevalent computing paradigm, Graph Anomaly Detection provides an effective solution to ensure the security of DT industrial systems. However, the existing unsupervised graph anomaly detection methods tend to treat multiple graph attributes in isolation during the reconstruction process, resulting in insufficient semantics and suboptimal reconstruction performance. To overcome these challenges, we propose a multiattribute contrastive learning framework, which realizes graph anomaly detection by capturing both graph attribute patterns and their hidden relationships. First, we use an improved multiattribute aligned reconstruction approach to represent the anomaly information effectively. Besides that, the positive instance aggregation-based contrastive constraints are proposed, which can reduce the loss generated by mappings between different data dimension in feature representation space. Finally, to verify our proposal, extensive experiments have been conducted on five benchmark datasets, and the results show that our method obtains the state-of-the-art performance.

In advanced technology nodes, the proliferation of process corners poses significant challenges in timing signoff, particularly in estimating wire-induced interconnect delay across process corners. This paper proposes a learning-based framework to perform cross-corner timing prediction efficiently and accurately. It seamlessly integrates learning-based reference corner selection and topology-aware interconnect timing prediction into the broader timing signoff steps and Engineering Change Order (ECO) processes. Unlike previous methods, it only requires information about one single known corner while accurately predicting all unknown corners. Evaluated on two mainstream industry processes, the proposed framework surpasses alternative machine learning models and existing strategies, with an impressive average accuracy enhancement of 62.6% and 95.3% respectively, and maintains a low mean absolute error (MAE) under 0.37ps and 0.01ps. Additionally, a faster version of the framework is developed to predict interconnect delay directly from a single extracted SPEF, yielding over 2× speedup. Moreover, the single-corner approach featured by the framework significantly accelerates ECO processes by over 10× compared to standard timing signoff flows. The proposed framework is also set to be open-sourced at a later date.

Utilizing cloud EDA for chip design allows access to on-demand high-performance computing (HPC) resources, significantly reducing development time and costs by eliminating the need for costly on-site infrastructure. Despite its benefits, cloud EDA faces significant challenges, primarily the lack of an effective cost model. A key issue is the absence of a mechanism for designers to accurately gauge the characteristics of their EDA jobs in cloud environment, as the design process involves a multitude of EDA tools and steps, often leading to the over or underestimation of needed computational resources. This problem is exacerbated by the varying computational demands of different designs and constraints. To bridge this knowledge gap, we introduce Elastic EDA, a methodology that harnesses machine learning (ML) to understand the characteristics of a design and its early stages, and to predict the computational needs for subsequent phases throughout the entire EDA flow. This approach effectively aligns design behaviors with computational resources, providing cost-efficient solutions for various cloud EDA scenarios. Compared to previous ML-based predictive frameworks for cloud EDA, the proposed method achieves over 60% higher prediction accuracy and supports various elastic computing environments, maximizing the efficiency of cloud re-sources. Compared to various baseline scheduling configurations in the cloud environment, the proposed framework achieves over 16% mean runtime improvement.

Advancements in peptidomics have revealed numerous small open reading frames with coding potential and revealed that some of these micropeptides are closely related to human cancer. However, the systematic analysis and integration from sequence to structure and function remains largely undeveloped. Here, as a solution, we built a workflow for the collection and analysis of proteomic data, transcriptomic data, and clinical outcomes for cancer-associated micropeptides using publicly available datasets from large cohorts. We initially identified 19 586 novel micropeptides by reanalyzing proteomic profile data from 3753 samples across 8 cancer types. Further quantitative analysis of these micropeptides, along with associated clinical data, identified 3065 that were dysregulated in cancer, with 370 of them showing a strong association with prognosis. Moreover, we employed a deep learning framework to construct a micropeptide-protein interaction network for further bioinformatics analysis, revealing that micropeptides are involved in multiple biological processes as bioactive molecules. Taken together, our atlas provides a benchmark for high-throughput prediction and functional exploration of micropeptides, providing new insights into their biological mechanisms in cancer. The HMPA is freely available at http://hmpa.zju.edu.cn.

A typical design flow is separated into front-end and back-end stages, incurring huge number of iteration loops between logic synthesis and place and route to close timing. This has been even worse in advanced technology where wire delay dominates timing. It becomes increasingly important to integrate physical awareness in the logic synthesis optimization processes to achieve better timing correlations. To tackle the physically-aware synthesis challenges, in this paper, we formulate the whole design flow as a multi-stage search problem, where informed search algorithms are utilized to perform efficient search with additional guidance. By incorporating a newly-developed learning-based routing-aware timing prediction model in the inform value function, a delay-driven physically-aware synthesis methodology called DDPAS is proposed, enabling efficient logic optimization with awareness of final routed design. The framework pairs with various search algorithms and learning-based strategies. Evaluation results show that the greedy search based DDPAS improves total negative slack (TNS) by over 58% and achieves over 7% power savings when compared to its counterpart, and the reinforcement learning (RL) based DDPAS delivers 65.6% improvement in terms of TNS and 12.1% power savings compared to a state of the art RL-based logic synthesis framework. Overall, DDPAS yields to better final QoR after routing and significantly reduces the timing closure cycles.