This paper presents a 12-bit, 700-MS/s pipeline ADC fabricated in TSMC 40-nm technology, with a focus on power optimization in residue amplifiers and comparator cells. The effective transconductance of the inter-stage amplifiers and comparators is optimized for the minimum power consumption while meeting CDAC matching requirements. The architecture consists of two 3.5-bit/stage blocks in cascade with a sub-range 6-bits flash ADC. A two-stage class AB residue amplifier with cascode output stage and complementary differential pairs is employed, effectively double its DC gain and capable of achieving twice the slew rate (SR) and gain-bandwidth product (GBW) compared to the conventional design with equivalent power consumption. The residue amplifier does not require specific frequency compensation since the cascode output stage and large load capacitor determine the dominant pole that is naturally separated from the pole generated at the output of the first stage. To further enhance ADC’s power efficiency, the multiplying digital-to-analog converter (MDAC) of the second stage is designed to enable the functionality of the subsequent sub-range 6-bit flash ADC. The two-step 6-bit backend stage resolves the last 3 MSBs and 3 LSBs sequentially, significantly reducing power consumption. A digital calibration scheme employing key DC test signals effectively correct gain and non-linearity errors. Experimental results for a 40nm CMOS prototype show that the proposed pipeline ADC achieves a Signal-to-Noise and Distortion Ratio (SNDR) of 69.2 dB and a Spurious-Free Dynamic Range (SFDR) of 81.5 dB at low input frequencies. 68.5 dB SNDR and 80.7 dB SFDR near the Nyquist frequency at 700 MS/s are achieved. The ADC core occupies an active area of$0.56~mm^{2}$and consumes 24.3 mW from a 1.2 V power supply. Near Nyquist frequency, the measured Schreier figure of merit is approximately 170.1 dB.

This article presents a 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) architecture that uses a 9-bit capacitive DAC (CDAC) and innovative techniques that include passive amplification circuitry without engaging active components and the strategic connection of a unity capacitor to multiple reference voltages, to achieve a total of 12 bits. The proposed passive amplification technique saves 27% of the ADC area through reducing the CDAC size by 50% compared to a conventional 10-bit CDAC +2-bit voltage reference design for a 12-bit resolution. Compared with the conventional 12-bit C-DAC SAR, the proposed SAR-ADC saves over 75% of the active area. The measurement results reveal that the core of the proposed ADC architecture dissipates 3 mW. Fabricated in a mainstream 40-nm CMOS technology, the proposed ADC attains SNDR/SFDR ratios as high as 63.5/72.13 dB for a 10-MHz sinusoidal test tone; the SAR active area is about$0.00966~\text {mm}^{2}$. Furthermore, this architecture yields favorable results regarding the Walden figure-of-merit of approximately 26.5 fJ/conv-step while maintaining Schreier FOM around 165.37 dB when measured at 10 MHz.

Researches using margin based comparison loss demonstrate the effectiveness of penalizing the distance between face feature and their corresponding class centers. Despite their popularity and excellent performance, they do not explicitly encourage the generic embedding learning for an open set recognition problem. In this paper, we analyse margin based softmax loss in probability view. With this perspective, we propose two general principles: 1) monotonically decreasing and 2) margin probability penalty, for designing new margin loss functions. Unlike methods optimized with single comparison metric, we provide a new perspective to treat open set face recognition as a problem of information transmission. And the generalization capability for face embedding is gained with more clean information. An auto-encoder architecture called Linear-Auto-TS-Encoder(LATSE) is proposed to corroborate this finding. Extensive experiments on several benchmarks demonstrate that LATSE help face embedding to gain more generalization capability and it boost the single model performance with open training dataset to more than 99% on MegaFace test.