Multiple intellectual property (IP) protections have emerged to defeat security threats in integrated circuit (IC) supply chain. Among these, logic locking is regarded as a promising IP protection for its security. A state-of-the-art work uses stripped-functionality logic locking (SFLL) technique with protected input patterns (PIPs) satisfying the distance of at least 2 (Dist2) property, or D2PIPs, for ensuring resilience against both input-output (I/O)-based and structural attacks. However, this approach has research challenges in scalability, flexibility, and security, as stated and discussed in our paper. Our paper solves these challenges by (i) utilizing a satisfiability modulo theories (SMT) solver and (ii) developing a secure circuit encoding scheme. SCONE, our secure logic locking technique, combines the two methods and meets all three challenges simultaneously. Our results show that SCONE improves scalability $\mathbf{3 5 0} \times$ on the IBEX processor (16 K gates) and remains resilient against five I/O or structural attacks. Index Terms-logic locking, encoding scheme, SMT solver.

The unauthorized duplication of design intellectual property (IP) and illegal overproduction of integrated circuits (ICs) are hardware security threats plaguing the security of the globalized IC supply chain. Researchers have developed various countermeasures such as logic locking, layout camouflaging, and split manufacturing to overcome the security threat of IP piracy and unauthorized overproduction. Logic locking is a holistic solution among all countermeasures since it safeguards the design IP against untrusted entities, such as untrusted foundries, test facilities, or end-users throughout the globalized IC supply chain. There are well-known logic locking techniques for combinational circuits with well-established security properties; however, their sequential counterparts remain vulnerable. Since most practical designs are inherently sequential, it is essential to develop secure obfuscation techniques to protect sequential designs. This paper proposes a sequential obfuscation technique, STATION, building on the principles of finite state machine encoding schemes. STATION is resilient against various attacks on sequential obfuscation–input-output (I/O) query attacks and structural attacks, including the ones targeting sequential obfuscation–which have broken all state-of-the-art sequential obfuscation techniques. STATION achieves good resilience and desired security against various I/O and structural attacks, which we ascertain by launching 9 different attacks on all tested circuits. Moreover, STATION ensures tolerable overheads in power, performance, and area, such as 8.75%, 1.22%, and 5.63% on the largest tested circuit, containing 102 inputs, 7 outputs, 6.1×104 gates, 7 flip flops, 100 states, and 3.0×103 transitions.

Logic locking acts as powerful countermeasure against piracy and reverse engineering attacks on the Integrated circuit (IC) supply chain. Stripped functionality logic locking (SFLL) represents the state-of-the-art in logic locking. SFLL delivers high resilience against certain attacks; however, it can protect only a small fraction of the design. Moreover, it fails to achieve a high corruption rate at the circuit outputs. In this paper, we explore strategies for deploying SFLL in a way that optimizes both corruption rate and resilience while protecting a large fraction of the design. The proposed joint optimization framework leverages the principles of VLSI testing to meet desired objectives cost-effectively.