In the above article [1], the errors were addressed. Due to a production error, several reference citations were mistakenly typeset as “[?].” The correct references are as follows. 1)To improve Trojan isolation, the approach proposed in [11] reorders the circuit’s scan chains to create physically segregated regions that can be more easily activated individually.2) The most straightforward of the metrics is Trojan-to-circuit activity ( $ TCA $ ), defined in [11] as $TCA(TP_{i}) =\frac{TA_{i}}{CA_{i}}$ , where $TP_{i}$ denotes the test pattern under evaluation, $TA_{i}$ denotes the number of active Trojan gates for $TP_{i}$ , and $CA_{i}$ denotes the number of active non-Trojan gates for $TP_{i}$ .3)We performed experiments on Trust-Hub benchmarks with combinational Trojans inserted within sequential designs [20], [21] to confirm the proposed test pattern generation as a viable approach.4)To evaluate the effectiveness of this adaptive flow, the proposed methodology is executed on five Trojan-inserted ISCAS benchmarks made available on the Trust-Hub website [20], [21].5)2) Considering Process Variation: To introduce process variation, we model interdie and intradie variation as normal distributions with a mean of 1 and respective magnitudes of $15\% = 3\sigma_{inter}$ and $ 5\% = 3\sigma_{intra}$ (similar to values used in [11] and [12]).6)An alternate design-based approach [11] changes the ordering of scan chains to improve the ability to isolate a given region of the design.

At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vminpose a risk of over-testing and production yield loss. This is particularly problematic if the Vminof the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmindebug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vminby preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vminby 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.

Pseudo-Exhaustive Physically-Aware Region (PEPR) testing, in its most general application, rasterizes the layout of a logic circuit into overlapping three-dimensional regions of user-defined size. Faults that correspond to the exhaustive testing of each subcircuit within a region are defined and used for automatic test pattern generation (ATPG), fault simulation, and diagnosis. Evaluation of tens of thousands of chip failures demonstrated the effectiveness of PEPR in capturing the exact behavior of defects.However, deployment of PEPR is challenged by the large number of faults produced for exhaustively testing each region. Analysis revealed that there are a small percentage of regions that require a significant number of faults. For instance, a 14nm test chip contains regions that require more than 32M faults to test. While it is certainly possible to define a region size that produces large subcircuits, we found that large subcircuits predominantly result from including the entirety of a cell when a region simply intersects a small portion of the cell. To remedy this situation, we have developed IC-PEPR, a novel intra-cell extension to PEPR that significantly reduces the number of resulting faults. Specifically, by exploiting equivalence within a cell, intra-cell components within a region are controlled to all possible values without applying all cell-level input patterns. Applying IC-PEPR testing reduces the number of faults for a commercial benchmark circuit by more than 100X. This reduction in fault count results in a corresponding reduction in ATPG run time (almost 50X reduction) and test set size (>10X reduction).

Logic circuit diagnosis is an essential tool for improving manufacturing yield. However, there is a significant disparity between the behavior predicted by conventional fault models and the actual behavior observed in failing circuits. This undermines the performance of diagnosis methodologies that rely on conventional fault models to characterize defect behavior. Recently, a parameterizable test metric called PEPR has demonstrated the ability to precisely bound defect behavior, even when it deviates from conventional fault model assumptions. This paper describes a novel diagnosis methodology that uses the PEPR metric to determine (i) the physical location of a defect and (ii) the precise changes to the logic functionality of the affected circuit in the form of a custom fault model. The methodology, called CHEF, is applied to over 700 fail logs from a 22nm industrial test chip. Results demonstrate CHEF precisely characterizes defects that conventional diagnosis cannot, specifically when failure behavior does not align with a conventional fault model. Furthermore, CHEF achieves a significant increase in diagnostic resolution compared to conventional diagnosis, more than doubling the number of failures with a physical resolution better than 1µm2. Finally, diagnostic patterns generated by CHEF demonstrate the capability to further refine defect characterization.

Recently, companies such as Google, Meta (Facebook), and Microsoft reported in the mainstream press about seemingly random errors which, initially undetected ("silently"), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermittently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?

It is well-known that understanding the behavior of silicon failures is an essential step in yield learning. It is also becoming more important for producing high-quality silicon due to the increasing number of defects detected fortuitously. In order to meet this need, a new approach for extracting the precise faulty function from defective logic circuits is described. The approach is applied to nearly a 1,000 14nm failures and one use case of the results on improving ATPG is discussed.

Debug of failing tests during new product introduction is a human-time-intensive task, requiring the focus of domain experts to develop and execute fact-finding experiments. In particular, complex failures in logic circuitry can be challenging to localize and characterize. The prior AAA (Automated, On-ATE AI) Debug Expert System operated on scan chain failures, using various debug methodologies to identify key information about the failure. This paper proposes Logic-AAA, an extension to AAA that uses the same framework to target failures in digital logic based on structural tests. Among the methods implemented in this system are failing flop identification for determining failure location, exhaustive backcone testing for determining failure behavior, and cross-voltage rail shmoo collection for determining test condition behavior. Logic-AAA can perform expert-like debug tasks in an automated fashion, which leads to significant resource savings and enables non-experts to perform complex debug.

Delay faults have become increasingly important in modern designs due to decreasing technology node size and increasing operation frequency. However, diagnosis of delay faults can be challenging since there are typically few failing bits in the test failures. In this work, a two-phase flow is presented to identify systematic delay failures and improve their corresponding diagnosis resolution. First, the subset relationships among test failures are analyzed to identify systematic defects. Then, representative test failures in the subset relationships are selected to diagnose the defect behavior. Experiments on two cores of an industrial design with three cases show over 33×, 69×, and 8× improvement on delay fault diagnosis resolution. Furthermore, the proposed technique can be easily integrated with commercial tools.

Scan chain diagnosis plays a key role in ramping up production yield. However, this is challenged by high test compression ratios of modern designs, increasing the probability of multiple faulty chains feeding the same compressor. In our analyzed silicon data, we observe that 8.76% of scan chain failures have such two faulty chains. We propose a technique to help address this problem, separating the superposition of chain fault effects to diagnose these chips. This technique first uses jump simulation to identify and classify failures that are attributable to only one of the faulty chains. It then uses commercial tools to diagnose the classified failures of each chain individually. Experiments are conducted on both simulated and silicon test data to show the efficacy of our technique, and the proposed method showed improvements over standard diagnosis with commercial tools in resolution (2.38 candidates) and accuracy (92.0%). This method was also applied on industrial chips with potentially systematic double faulty chain failures.

Recent reports indicate that existing fault models and test metrics result in substantial manufacturing test escapes that cause major system-level challenges such as silent data corruption resulting from incorrect computations. Such test escapes are often detected today after system deployment (e.g., in the field) using a variety of synthetic and application workloads. In this work, a new test metric is investigated for detecting defects that escape existing test approaches. PEPR (Pseudo-Exhaustive Physically-Aware Region) testing comprehensively analyzes both the physical layout and the logic netlist to identify single- or multi- output sub-circuits. The resulting sub-circuits are exhaustively tested to detect timing-independent combinational (TIC) defects. Analyses demonstrate that PEPR-based scan tests detect TIC defects perfectly (100%) when examining fail data from over 30,000 14nm failing chips. In contrast, existing fault models and test metrics might result in up to 95 % of TIC defects being detected fortuitously. Strategies for addressing increased test pattern count resulting from the pseudo-exhaustive nature of PEPR testing are also discussed.

Debug of failing tests during new product introduction is a human-time-intensive task, requiring the focus of domain experts to develop and execute fact-finding experiments. With the increasing size and complexity of modern integrated circuit products, and the increasing size of company product portfolios, it is challenging and taxing for these few experts to support all required debug. To overcome this bottleneck of limited expertise, we propose AAA, a rule-based expert system to perform automated, on-the-tester debug of failing tests. The system is designed to replicate the typical procedure followed by an expert, including the dynamic creation and application of targeted debug tests, collection of on-tester silicon failure results, and analysis of the results to improve root-cause understanding. AAA performance is demonstrated on industrial chips with scan chain failures.

Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginalities, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques is demonstrated on two industrial designs in cutting-edge process nodes and verified by targeted analysis and testing. The number of suspects is reduced by 3.1x and 575.2x on average. The proposed techniques can be implemented using existing commercial diagnosis tools with runtime overheads below 1%.

As society becomes increasingly reliant on products and systems that make use of integrated circuits, the defense against potential hardware Trojan attacks by an untrusted foundry becomes an important part of any certification flow for critical components. The slew of recent proposals notwithstanding, a satisfactory solution is still wanting as the solutions offered heretofore either require impractical design/test pattern cost or deliver insufficient detection capabilities, primarily challenged by the noise induced by process variation. The methodology put forth by this proposal aims to remedy this, leveraging an adaptive approach that applies superposition to perform a fine-grained circuit analysis and expose any extant Trojan circuitry. Iterative test pattern modifications, circuit response analysis, and adaptive decision-making are deployed, all embedded within the design-for-test and test pattern cost paradigms of a common industrial circuit. We demonstrate the efficacy of this technique on standard Trust-Hub benchmark circuits with combinational Trojans inserted in sequential designs, showing significant improvement over prior techniques. We also explore the potential cost-benefit tradeoffs that exist within such a methodology, with the intent to provide an efficient solution for an array of potential product markets. This methodology provides a reliable and effective means for Trojan detection, addressing an important piece of the overall circuit certification puzzle.

Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.

Current methods for the detection of hardware Trojans inserted by an untrusted foundry are either accompanied by unreasonable costs in design/test pattern overhead, or return results that fail to provide confident trustability. The challenges faced by these side-channel techniques are primarily a result of process variation, which renders pre-silicon expectations nearly meaningless in predicting the behavior of a manufactured IC. To overcome this hindrance in a cost-effective manner, we propose an easy-to-implement test pattern-based approach that is self-referential in nature, capable of dissecting and understanding the characteristics of a given manufactured IC to hone in on aberrant measurements that are demonstrative of malicious Trojan hardware. By leveraging the superposition principle to cancel out non-Trojan noise, we can isolate and magnify Trojan circuit effects, all within a regime considerate of practical test and design-for-test infrastructures. Experimental results performed on Trust-Hub benchmarks demonstrate the proposed method provides a clear and significant boost in our ability to confidently certify manufactured ICs over similar state-of-the-art techniques.

While many side-channel methods have been proposed for detecting hardware Trojans inserted by an untrusted foundry, they are challenged in the face of process variation noise. The impacts of process variation have forced researchers to propose costly design enhancements to improve detection as a counter to the deficiency of current easy-to-implement test pattern-based methods. To overcome process variation noise with no design cost, we propose a novel self-referencing adaptive approach based on test pattern construction, which learns from and conforms to device characteristics to maximally magnify the Trojan signal. Through iterative test pattern modifications, response analyses, and decision-making, we can pursue suspicious behaviors and increase the likelihood of Trojan detection. Experiments on Trust-Hub Trojan circuit benchmarks show the efficacy of this technique, magnifying an equivocal starting signal 22 to 130 to deliver crisp resolution to the question of Trojan existence.