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Marco Antonio Merlini

dblp:268/2165 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Hardware accelerators and domain-specific architectures · 44% Cloud and datacenter computing · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA debugging
0.512021
Interactive Debugging at IP Block Interfaces in FPGAs · FPGA 2021
Hardware accelerators and domain-specific architectures
interactive debugging
0.512021
Interactive Debugging at IP Block Interfaces in FPGAs · FPGA 2021

Methods — techniques the papers use, named apart from their topics

debug governor · 0.5
YearPublicationVenuePosition
2021 Interactive Debugging at IP Block Interfaces in FPGAs
abstract
Recent developments have shown FPGAs to be effective for data centre applications, but debugging support in that environment has not evolved correspondingly. This presents an additional barrier to widespread adoption. This work proposes Debug Governors, a new open-source debugger designed for controllability and interactive debugging that can help to locate issues across multiple FPGAs.
Marco Antonio Merlini, Isamu Poy, Paul Chow
FPGA1
2020 FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark
abstract
Wireshark-based debugging can be performed on ordinary desktop computers at 1G speeds, but only powerful computers can keep up with 10G. At 100G, this debugging becomes virtually impossible to perform on a single machine.This work presents FFShark, a Fast FPGA implementation of Wireshark. The result is a compact, relatively inexpensive passthrough device that can be inserted into any running 100G network. Packets will travel through FFShark with no interruption and minimal additional latency. A developer can send standard Wireshark filter programs to the FFShark device at any time; packets that satisfy the filter will be copied and sent back to the developer’s workstation over a separate connection.We show that our open source passthrough device has lower latency than commercial 100G switches, and that our design is already capable of handling 400G speeds.
Juan Camilo Vega, Marco Antonio Merlini, Paul Chow
FCCM2