Fixing bugs in hardware design code has become a challenging task due to the increasing complexity of modern circuit designs. As a result, automated program repair techniques have been proposed to synthesize patches for bugs in hardware designs and achieved promising results. However, existing techniques are still limited in synthesizing expressions for complex bugs. In this work, we explore the possibility of addressing complex bugs by proposing SREPAIR, a novel symbolic regression-based repair technique. The key novelty of SREPAIR lies in three aspects: 1) we propose a novel expression modification encoding that enables fine-grained adjustments to buggy expressions. 2) we introduce expression synthesis-based templates that allow for flexible and expressive repairs. 3) we develop a novel symbolic regression network-based synthesis algorithm that effectively synthesizes complex expressions. Experimental results on the four peer-reviewed datasets demonstrate that SREPAIR correctly fixes 56 bugs out of 112 bugs, which achieves 43.6% and 194.7% improvement over the previous state-of-the-art RTL-REPAIR (39 bugs) and CIRFIX (19 bugs). To evaluate the generalizability of SREPAIR, we further construct an augmented dataset of 282 bugs by mutating hardware designs. SREPAIR shows its better generalizability by correctly fixing 127 bugs, reaching 217.5% improvement over the best approach.

Gate-level fault simulation is a critical step in design for test and functional safety verification of the chip design process, essential to ensuring circuit reliability. As chip complexity grows for mission-critical applications such as autonomous vehicles, medical devices, and military systems, the efficiency of fault simulation increasingly becomes a bottleneck in the chip’s time-to-market. However, existing methods often suffer from computational redundancy, inefficiencies in memory access, or failure to optimize performance for specific CPU hardware platforms. This paper proposes DomSim, a hardware-aware hybrid fault simulation method that combines compiled simulation and event-driven simulation with an optimized computation-to-memory-access ratio. By utilizing circuit information and hierarchical structure provided by dominator trees, DomSim achieves high-quality circuit partitioning, optimizing hardware resource utilization and memory access locality. Furthermore, a parameter adjustment strategy tailored to hardware capabilities and circuit characteristics enables adaptive optimization. Extensive experiments show that DomSim surpasses a commercial tool by 10.29× on average. Further experiments demonstrate that DomSim exhibits good adaptability across different hardware platforms and circuits, highlighting the superiority of our method.

With the advancement of integrated circuit (IC) technology, the sensitivity to delay defects has significantly increased, rendering Transition Fault (TF) testing crucial for ensuring chip quality. However, as the complexity of IC designs increases, existing pattern parallelization methods are not flexible in detecting multi-cycle faults. In addition, the growing demand for simulation memory exacerbates inefficient memory access, becoming another critical bottleneck. This paper introduces ETPG (Efficient Transition fault simulation via dual-strategy Pattern parallelism and Gate restructuring), a novel TF simulation algorithm based on multi-dimensional optimization. The key innovations include an adaptive dual-strategy pattern parallel strategy that dynamically optimizes parallelization based on test pattern characteristics, enhancing efficiency and multi-cycle fault detection capability; a dual-dimension gate restructuring method that optimizes memory storage order, significantly reducing memory access time, particularly beneficial for large-scale circuits; and a collaborative mechanism between pattern processing and circuit storage optimization, achieving comprehensive performance improvements at both algorithmic and memory access levels. Experimental results demonstrate ETPG's significant performance improvements across various circuit scales, particularly for larger circuits. Compared to the synopsys commercial tool testmax (TMAX), ETPG achieves average speedups of 2.846× for circuits below 100k gates and 4.428× for circuits above 100k gates.

In automatic test pattern generation (ATPG), SAT-based methods are typically used to complement structural approaches, especially for addressing hard-to-detect faults. However, as the size and complexity of circuits grow, SAT-based ATPG faces challenges like pattern inflation and excessive runtime, limiting its overall performance. The key problem lies in the fact that current mainstream SAT solvers perform complete assignments for all primary inputs of the fault’s transitive fanin cone without considering the detection of other faults, making test compaction extremely difficult and time consuming. In this paper, a novel SAT solver PA-MiniSat is proposed, which is capable of generating partial assignments for solving variables and significantly reduces the number of specified bits in test cubes. As an extension of MiniSat, it employs a full-literal watching technique and a circuit-adapted heuristic branching strategy, achieving overall improved performance in ATPG. Based on PA-MiniSat, a hybrid ATPG framework PastATPG is proposed for better test compaction, which tightly integrates structural algorithms with the SAT solver into the unified test compaction flow. Experimental results demonstrate that our method outperforms other SAT solvers in pattern compaction and, in some cases, even surpasses commercial ATPG tools in terms of speed. The code is available at https://github.com/sklp-eda-lab/PastATPG.

Deep learning has significantly advanced Electronic Design Automation (EDA), with circuit representation learning emerging as a key area for modeling the relationship between a circuit’s structure and functionality. Existing methods primarily use either Large Language Models (LLMs) for Register Transfer Level (RTL) code analysis or Graph Neural Networks (GNNs) for netlist modeling. While LLMs excel at high-level functional understanding, they struggle with detailed netlist behavior. GNNs, however, face challenges when scaling to larger sequential circuits due to long-range information dependencies and insufficient functional supervision, leading to decreased accuracy and limited generalization. To address these challenges, we propose MOSS, a multimodal framework that integrates GNNs with LLMs for sequential circuit modeling. By enhancing D-type Flip-Flop (DFF) node features with embeddings from fine-tuned LLMs on RTL code, we focus the GNN on critical anchor points, reducing reliance on long-range dependencies. The LLM also provides global circuit embeddings, offering efficient supervision for functionality-related tasks. Additionally, MOSS introduces an adaptive aggregation method and a two-phase propagation mechanism in the GNN to better model signal propagation and sequential feedback within the circuit. Experimental results demonstrate that MOSS significantly improves the accuracy of functionality and performance predictions for sequential circuits compared to existing methods, particularly in larger circuits where previous models struggle. Specifically, MOSS achieves a $\mathbf{9 5. 2 \%}$ accuracy in arrival time prediction.

As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage, requiring extensive gate-level fault simulations. However, for large-scale industrial sequential circuits, these simulations are time-consuming, creating a significant bottleneck in chip development. Prior approaches have focused on reducing computational complexity and optimizing CPU hardware usage by minimizing redundant computations during fault propagation and leveraging bit-level parallel processing capabilities. Techniques like parallel-pattern and event-driven simulations have improved performance in combinational circuits but face limitations in sequential circuits due to timing dependencies within loops. The challenge lies in parallelizing simulations across different cycles without violating these dependencies, which is exacerbated by the complex feedback structures in SCCs. In this work, we propose a novel parallel-pattern fault simulation framework that combines loop fusion with efficient event traversal to accelerate sequential circuit simulations. By compiling simple loops into larger nodes, we reduce the number of feedback events without introducing excessive redundancy. For larger SCCs, we develop specialized algorithms for selecting loop entrance nodes based on indegree analysis and implement the lazy propagation strategy for internal nodes. This approach minimizes simulation events caused by inaccurate predictions and reduces overhead associated with false event propagation. We integrate these techniques into our simulation framework, EPICS, which strategically mixes compiled and event-driven simulations to optimize performance. Experimental results demonstrate that EPICS achieves a $5.94 \times$ speedup over state-of-the-art commercial tool while maintaining the same fault coverage.

As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric for functional safety is achieving a sufficient fault coverage. To meet this requirement, extensive time-consuming fault simulation of the RTL code is necessary during the chip design phase. The main overhead in RTL fault simulation comes from simulating behavioral nodes (always blocks). Due to the limited fault propagation capacity, fault simulation results often match the good simulation results for many behavioral nodes. A key strategy for accelerating RTL fault simulation is the identification and elimination of redundant simulations. Existing methods detect redundant executions by examining whether the fault inputs to each RTL node are consistent with the good inputs. However, we observe that this input comparison mechanism overlooks a significant amount of implicit redundant execution: although the fault inputs differ from the good inputs, the node's execution results remain unchanged. Our experiments reveal that this overlooked redundant execution constitutes nearly half of the total execution overhead of behavioral nodes, becoming a significant bottleneck in current RTL fault simulation. The underlying reason for this overlooked redundancy is that, in these cases, the true execution paths within the behavioral nodes are not affected by the changes in input values. In this work, we propose a behavior-level redundancy detection algorithm that focuses on the true execution paths. Building on the elimination of redundant executions, we further developed an efficient RTL fault simulation framework, Eraser. Experimental results show that compared to commercial tools, under the same fault coverage, our framework achieves a 3.9 × improvement in simulation performance on average.

With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes more critical. Ensuring chip functional safety requires performing a large number of time-consuming RTL fault simulations during the design phase, significantly increasing the verification cycle. To meet time-to-market demands while ensuring thorough chip verification, parallel acceleration of RTL fault simulation is necessary. Due to the dynamic nature of fault propagation paths and varying fault propagation capabilities, task loads in RTL fault simulation are highly imbalanced, making traditional single-dimension parallel methods, such as structural-level parallelism, ineffective. Through an analysis of fault propagation paths and task loads, we identify two types of tasks in RTL fault simulation: tasks that are few in number but high in load, and tasks that are numerous but low in load. Based on this insight, we propose a two-dimensional parallel approach that combines structural-level and fault-level parallelism to minimize bubbles in RTL fault simulation. Structural-level parallelism combining with work-stealing mechanism is used to handle the numerous low-load tasks, while fault-level parallelism is applied to split the high-load tasks. Besides, we deviate from the traditional serial execution model of computation and global synchronization in RTL simulation by proposing a unified computation/global synchronization scheduling approach, which further eliminates bubbles. Finally, we implemented a parallel RTL fault simulation framework, RIROS. Experimental results show a performance improvement of 7.0× and 11.0× compared to the state-of-the-art RTL fault simulation and a commercial tool.

The "Shift-Left" Design-for-Test (DFT) paradigm has gained significant attention in recent years, enabling early-stage testability enhancement at the Register Transfer Level (RTL) to optimize Power-Performance-Area-Testability (PPAT) trade-offs and accelerate Time-to-Market (TTM). However, existing methods struggle to perform quantitative testability analysis at the RTL stage, particularly in Partial Scan Selection (PSS) and Test Point Insertion (TPI), due to the lack of structured netlist representations and cross-stage optimization. To address this challenge, we propose TESLA, a multi-LLM collaboration framework that autonomously performs PSS and TPI at the RTL stage. TESLA leverages the semantic understanding capabilities of Large Language Models (LLMs) to analyze RTL Verilog code and optimize testability without requiring synthesis. Two key data augmentation strategies are introduced for efficient Instruction Tuning: (1) back-annotating heuristic PSS results from the synthesized netlist to RTL, and (2) utilizing advanced LLMs guided by DFT knowledge to generate synthetic RTL TPI training data. Furthermore, we integrate Direct Preference Optimization (DPO) to refine LLM decision-making, incorporating real feedback from commercial EDA tools to align optimization objectives with practical testability metrics. The experimental results demonstrate that our proposed approach achieves better test coverage compared to other RTL stage PSS and TPI combination schemes on the majority of circuits in the RTLLM benchmark, while also reducing the number of patterns for a significant portion of the circuits. On the larger, hierarchical OpenCores benchmark, our approach surpasses the solution combining heuristic PSS and commercial DFT tool’s TPI, achieving improvements on the same two test metrics.

As integrated circuits grow in complexity, test point insertion (TPI) has become vital for enhancing testability and improving reliability in design for test (DFT). Recent studies have shown the effectiveness of deep learning-based TPI using graph neural networks (GNNs) in improving test quality. However, the high cost of collecting training data, incomplete capture of the intrinsic characteristics of circuits, and the vast search space in large circuits hinder the performance of existing intelligent approaches. This paper introduces HighTPI, a two-stage learning approach for TPI to effectively reduce the number of test patterns, which leverages hierarchical graph representation by constructing a hypergraph based on hypernodes in fanout-free regions (FFRs). HighTPI better captures multi-fanout reconvergence information while lowering the cost of obtaining ground-truth labels due to the smaller scale of the FFR-based hypergraph. Two specialized GNNs are designed in stage I to select candidate insertion points for observation and control points, respectively. This integration of expert knowledge through supervised learning helps guide the reinforcement learning process in stage II, mitigating the challenges of sparse rewards and a large decision space. The experimental results demonstrate that HighTPI outperforms other TPI methods in terms of the trade-off between pattern reduction and fault coverage enhancement.

Fast simulation is vital for efficient digital design, especially for safety-critical applications, where functional safety verification is paramount. However, existing gate-level event-driven simulators often encounter performance challenges attributed not only to inefficient memory access, but also to redundancy events in sequential elements during event-driven algorithms. In this paper, we introduce a memory-efficient, low-redundancy event-driven simulation framework to accelerate sequential circuit simulation. Firstly, we propose an event-based memory layout approach that fully considers memory access characteristics within and between logic levels to enhance the spatial locality of simulators. Secondly, we present an event trace approach tailored for flip-flops to reduce event redundancies that hinder simulator performance. Comparative experiments demonstrate that our proposed optimization strategies deliver an average performance improvement of 1.9× for logic simulation and 1.4× for fault simulation.

The use of cross-scheme fully homomorphic encryption (FHE) in privacy-preserving applications present to be a new challenge to hardware accelerator design. Existing accelerator architectures with customized polynomial-level operator abstraction fail to efficiently handle hybrid FHE schemes due to the mismatch between computational demands and available hardware resources under various parameter settings. In this work, we propose a new accelerator architecture that consists of a novel finer-grained low-level operator, i.e., Meta-OP, that not only mathematically supports a diverse range of polynomial operations, but is also hardware-friendly for accelerator design without complex topological logic. We then design a new slot-based data management scheme to efficiently handle the distinct memory access patterns over the Meta-OP. With a slot-based data management approach, Alchemist can accelerate both arithmetic and logic FHE workloads with high hardware utilization rates. In the experiment, we show that Alchemist is up to 24,829X faster than CPU. For arithmetic FHE, compared with the SOTA ASIC accelerators, Alchemist achieves a 29.4X performance per area improvement on average. For logic FHE, compared with the SOTA ASIC accelerators, Alchemist achieves a 7.0X overall speed up on average.

Fault simulation is a fundamental component in the design for testability (DFT) processes, especially in automatic test pattern generation (ATPG). Various approaches have been proposed to enhance the efficiency of fault simulation on multi-core systems. However, these approaches have not taken full consideration of the intrinsic characteristics of deterministic patterns. Deterministic patterns are generated by ATPG and are predominantly employed in practical applications rather than random patterns. In this paper, we introduce DDP-Fsim, a fast and scalable fault simulator on multi-core systems. DDP-Fsim capitalizes on the distinctive nature of deterministic patterns, wherein a small subset of patterns can effectively detect the majority of faults. Initially, DDP-Fsim parallels in fault dimension by dynamically scheduling fanout-free regions (FFR) to handle easy-to-detect faults. Subsequently, it parallels in pattern dimension by dynamically scheduling patterns to address the remaining hard-to-detect faults. Experiments demonstrate that on a 24-core system, DDP-Fsim is 10× faster than the commercial tools for full-scan circuits and deterministic patterns. Additionally, DDP-Fsim with 24 cores achieves an average speed-up of 16× compared to its single-core execution, while the commercial tools with 24 cores achieves only 3×-6× speed-up than their single-core execution. This indicates the significantly superior scalability for DDP-Fsim.

Static test compaction aims to reduce the number of generated test patterns after automatic test pattern generation (ATPG) to enable one pattern to detect more faults. However, existing traditional algorithms require the establishment and maintenance of a fault detection profile to obtain essential faults, identified as those detectable exclusively by a single pattern (denoted as 1-D), incurring substantial computational overhead. We propose a novel fault gates classification approach based on graph convolutional network (GCN). By categorizing fault gates into with and without hard-to-detect faults, we selectively construct a partial fault detection profile only for the fault gates with hard-to-detect faults. Partial fault detection profile effectively reduces the time spent on establishing and maintaining it, as well as the time cost of obtaining essential faults. The experiment shows that our improved method can increase pattern reduction efficiency while accelerating, and its impact on fault coverage can be ignored. Compared with the original algorithm, the maximum acceleration ratio is 6.44×, and the number of patterns is reduced by up to 20.68%.

In applications such as automotive chips that require high service responsiveness, ensuring the functional safety of electronic systems is crucial. The prevalent method involves conducting Failure Modes, Effects, and Diagnostic Analysis (FMEDA) and fault simulation at the design verification stage to assess safety levels. However, existing approaches primarily analyze at the register transfer level (RTL), which does not reflect the actual structure of chips where faults occur at the gate level, resulting in inaccuracies. This is due to the slower analysis speed at the gate level, making it challenging to balance precision with speed, thus defaulting to RTL for simulation. To address these challenges, we propose an innovative method for functional safety analysis and verification that integrates advanced gate-level fault simulation technology with FMEDA techniques. Our approach is based on an enhanced gate-level FMEDA framework, enabling deeper and more accurate safety performance analysis. Through experimental verification, our method has proven to be over 3 times faster than commercial tools in fault simulation, significantly enhancing the reliability and speed of the functional safety process. Ultimately, our research provides rapid and precise safety analysis and verification at the gate level for high-risk applications like automotive chips, offering robust technical support and practical guidelines for advancing functional safety technology in this sector.

Class-agnostic binary segmentation identifies objects that are similar or very different from the complex background, including salient object detection (SOD) and camouflage object detection (COD). Most existing models only focus on a specific type of foreground and background segmentation by employing the global modeling ability of transformers, without explicitly explaining or eliminating the discrepancy between these two different distributions. They also suffer from inefficient local feature learning and inadequate feature aggregation. To make binary segmentation research more accessible and trivially generalized, we introduce a novel unified uncertainty-aware paradigm, called uncertainty-aware feature reassembly (UAFer). Specifically, the Spatial Feature Reassembly (SFR) module is presented to formulate the uncertainty of binary segmentation map as the variance of generalized Bernoulli distribution and entropy from two perspectives. Our transformer-based model is then trained to prioritize regions of higher certainty, obtaining more confident and accurate predictions during the feature upsampling. Moreover, the Channel Feature Reassembly (CFR) with adjacent feature aggregation is designed to facilitate an iterative exploration of channel integrity. This iterative learning process enhances the interaction of neighboring channel features; thus, improving universal object information decoding efficiency. Extensive quantitative and qualitative evaluations demonstrate that our proposed UAFer consistently outperforms the state-of-the-art models across three challenging domains including SOD, COD, and polyp segmentation (POLYP). The implementation codes for our approach will be publicly available at https://github.com/zihaodong/UAFR.

While Federated learning (FL) is attractive for pulling privacy-preserving distributed training data, the credibility of participating clients and non-inspectable data pose new security threats, of which poisoning attacks are particularly rampant and hard to defend without compromising privacy, performance or other desirable properties. In this paper, we propose a self-purified FL (SPFL) method that enables benign clients to exploit trusted historical features of locally purified model to supervise the training of aggregated model in each iteration. The purification is performed by an attention-guided self-knowledge distillation where the teacher and student models are optimized locally for task loss, distillation loss and attention loss simultaneously. SPFL imposes no restriction on the communication protocol and aggregator at the server. It can work in tandem with any existing secure aggregation algorithms and protocols for augmented security and privacy guarantee. We experimentally demonstrate that SPFL outperforms state-of-the-art FL defenses against poisoning attacks. The attack success rate of SPFL trained model remains the lowest among all defense methods in comparison, even if the poisoning attack is launched in every iteration with all but one malicious clients in the system. Meantime, it improves the model quality on normal inputs compared to FedAvg, either under attack or in the absence of an attack.

While the integration of Knowledge Distillation (KD) into Federated Learning (FL) has recently emerged as a promising solution to address the challenges of heterogeneity and communication efficiency, little is known about the security of these schemes against poisoning attacks prevalent in vanilla FL. From recent countermeasures built around KD, we conjecture that the way knowledge is distilled from the global model to the local models and the type of knowledge transfer by KD themselves offer some resilience against targeted poisoning attacks in FL. To attest this hypothesis, we systematize various adversary agnostic state-of-the-art KD-based FL algorithms for the evaluation of their resistance to different targeted poisoning attacks on two vision recognition tasks. Our empirical security-utility trade-off study indicates surprisingly good inherent immunity of certain KD-based FL algorithms that are not designed to mitigate these attacks. By probing into the causes of their robustness, the KD space exploration provides further insights into the balancing of security, privacy and efficiency triad in different FL settings.

Covert transmission is investigated for a cooperative deception strategy, where a cooperative jammer (Jammer) tries to attract a multi-antenna adversary (Willie) and degrade the adversary’s reception ability for the signal from a transmitter (Alice). For this strategy, we formulate an optimization problem to maximize the covert rate when three different types of channel state information (CSI) are available. The total power is optimally allocated between Alice and Jammer subject to the Kullback-Leibler (KL) divergence constraint, which can be expressed analytically and be widely used as a covertness measurement. Different from the existing literature, in our proposed strategy, we also determine the optimal transmission power at the jammer when Alice is silent, while existing works always assume that the jammer’s power is fixed. Specifically, we apply the S-procedure to convert infinite constraints into linear-matrix-inequalities (LMI) constraints. When statistical CSI at Willie is available, we convert double integration to single integration using asymptotic approximation and substitution method. Finally, our simulation results show that for the proposed strategy, the covert rate is increased with the number of antennas at Willie. Moreover, compared to the benchmark, our proposed strategy is more robust in the presence of imperfect CSI.

To prevent private training data leakage in Federated Learning systems, we propose a novel secure aggregation scheme based on seed homomorphic pseudo-random generator (SHPRG), named SASH. SASH leverages the homomorphic property of SHPRG to simplify the masking and demasking scheme, which for each of the clients and for the server, entails a overhead linear w.r.t model size and constant w.r.t number of clients. We prove that even against worst-case colluding adversaries, SASH preserves training data privacy, while being resilient to dropouts without extra overhead. We experimentally demonstrate SASH significantly improves the efficiency to 20× over baseline, especially in the more realistic case where the numbers of clients and model size become large, and a certain percentage of clients drop out from the system.

With the rapid development of deep learning techniques, the security issue for Neural Network (NN) systems has emerged as an urgent and severe problem. Hardware Trojan attack is one of the threatens, which provides attackers backdoors to control the prediction results of NN systems. This paper proposes a sequence triggered hardware Trojan. Normal images but with specific sequence are used to trigger the hardware Trojan and let attackers fully control the prediction results. This kind of trigger is not only robust to image pre-processing, but also unrecognizable by human beings. In comparison with existing hardware Trojan design, it is more practical and less hardware overhead. The experiments on MNIST, CIFAR100, and ISLVRC show that the proposed hardware Trojan is rarely triggered in normal working status while the hardware cost is reduced by 19X.