Associative processors (APs) are massively-parallel in-memory SIMD accelerators. While fairly well-known, APs have been revisited in recent years due to the proliferation of data-centric computing, and specifically, processing using memory. APs are based on Content Addressable Memory and utilize its unique ability to simultaneously search the entire memory content for a query pattern to implement massively parallel computations in memory. Several memory infrastructures have been considered for associative processing, including static CMOS, resistive, magnetoresistive, ferroelectric and even NAND flash memories. While all of these have certain merits (speed and low energy consumption for static CMOS, density for resistive and ferroelectric memories), they also face challenges (low density for static CMOS and magnetoresistive, limited write endurance and high write energy for resistive and ferroelectric memories), which limit the scalability and usefulness of APs. This work introduces GainP, an AP based on silicon-proven Gain Cell embedded DRAM (GCeDRAM). The latter combines relatively high density (compared to static CMOS memory) with low energy, high speed, practically unlimited endurance and low production costs (compared to emerging memory technologies). Using sparse-by-sparse matrix multiplication, we show that GainP outperforms high-performance CPU and GPU by 825 × and 41 × . We also show that GainP outperforms state-of-the-art processing-in-memory sparse matrix multiplication accelerators GAS, OuterSPACE and MatRaptor by 128 × , 125 × and 16 × , respectively, and provides average energy benefits of 96 × , 95 × and 15 × , respectively.

This work proposes a novel platform for bringing a project from the concept to the tapeout stage in a short amount of time. An open-source and extendable RISC-V architecture is exploited to build a small area footprint core. This leads the research platform to be flexible in terms of design integration, while also allowing fast design cycles of research chips.

Modern SoCs area and power budgets are often dominated by embedded memories on board of the chip. Gain-cell embedded DRAM is a dense, low power memory solution, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. This work presents a novel gain cell design, with robust dual read mechanism, exploiting GC-eDRAM characteristics for double write throughput, supporting low cost hidden refresh mechanism and 100% array availability, providing continuous 1W1R functionality. A 16 kbit memory macro was implemented in 65nm bulk technology offering up- to 20% reduction in bitcell area compared to standard SRAM solution, and up to 3 x area reduction compared to 1R1W memory solutions.

Operating circuits under cryogenic conditions is effective for a large spectrum of applications. However, the refrigeration requirement for the cooling of cryogenic systems introduces serious issues in terms of power dissipation. Gain-cell embedded dynamic random access memory (GC-eDRAM) is a low-area, logic-compatible embedded memory alternative to static random access memory (SRAM), which has the potential to provide ultralow-power operation under cryogenic conditions due to the lower leakages at these temperatures. In this article, we present the first comparative design exploration of GC-eDRAM under cryogenic conditions performed with transistor models characterized based on actual silicon measurements under temperatures as low as 77 K. Our study shows that the two-transistor (2T)-based GC-eDRAM configurations turn out to be the best solutions for very low-temperature operation. In particular, the 2T mixed GC-eDRAM configurations allow read sensing margin improvements (up to 99%) within the 2T-based configurations while at the same time excel in terms of data retention time (+44%) and power consumption (-27%) when compared to more complex GC-eDRAM topologies. Moreover, even better improvements in terms of area (-73%), leakage power (-97%), retention power (-76%), and energy (-66%) are observed when compared to conventional 6T-SRAM.

The emergence of autonomous applications, vision and information systems, and the shift from charge coupled devices (CCD) to complementary metal oxide silicon (CMOS) have led to significant advances in the image sensing field by extending research and development of new devices to the 3D sensing and neuromorphic functions field. We present a new weight-based operating concept for the current assisted photonic demodulator (CAPD) device and show how it can be used in future neuromorphic sensors. The new photodiode is capable of variably dividing the photo-generated charges amongst the surrounding pixels as well as real-time feed-backing between neighboring pixels. TCAD simulations are performed and analyzed to verify the new design's feasibility. A customized pixel circuit and pixel array which support the new photodiode design and operation concept are proposed as well as setups for averaging and edge detection functionalities.

Embedded memories occupy an increasingly dominant portion of the area and power budgets of modern SoCs and are also a limiting factor in VDDscaling. GC-eDRAM is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires an additional boosted voltage supply for successful write operations. This work presents a novel technique that uses the same negative voltage applied to the write port in many GC-eDRAMs topologies to expedite the read operation and/or further increase the DRT by using it during read operations. An 8 kbit memory macro was implemented in a 28nm FD-SOI technology, demonstrating over 20× read latency reduction, an order-of-magnitude longer DRT, and up-to 4 order-of-magnitude lower retention power consumption over a conventional 2T GC-eDRAM.