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Jin Si

dblp:269/5094 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Computer networks · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Processor architecture and microarchitecture · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.812024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning · ASPLOS (3) 2024
Hardware accelerators and domain-specific architectures › sparsity exploitation
sparse tensor accelerator
0.812024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning · ASPLOS (3) 2024
Processor architecture and microarchitecture › instruction set architecture › instruction set customization
domain-specific ISA
0.212024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning · ASPLOS (3) 2024
Processor architecture and microarchitecture
instruction set architecture
0.212024
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning · ASPLOS (3) 2024

Methods — techniques the papers use, named apart from their topics

sparse fiber tree · 0.8instruction-driven architecture · 0.8einstein summation · 0.8
YearPublicationVenuePosition
2025 Inductive Subgraph Embedding for Link Prediction
abstract
Abstract Link prediction, which aims to infer missing edges or predict future edges based on currently observed graph connections, has emerged as a powerful technique for diverse applications such as recommendation, relation completion, etc. While there is rich literature on link prediction based on node representation learning, direct link embedding is relatively less studied and less understood. One common practice in previous work characterizes a link by manipulate the embeddings of its incident node pairs, which is not capable of capturing effective link features. Moreover, common link prediction methods such as random walks and graph auto-encoder usually rely on full-graph training, suffering from poor scalability and high resource consumption on large-scale graphs. In this paper, we propose Inductive Subgraph Embedding for Link Prediciton (SE4LP) — an end-to-end scalable representation learning framework for link prediction, which utilizes the strong correlation between central links and their neighborhood subgraphs to characterize links. We sample the “link-centric induced subgraphs” as input, with a subgraph-level contrastive discrimination as pretext task, to learn the intrinsic and structural link features via subgraph classification. Extensive experiments on five datasets demonstrate that SE4LP has significant superiority in link prediction in terms of performance and scalability, when compared with state-of-the-art methods. Moreover, further analysis demonstrate that introducing self-supervision in link prediction can significantly reduce the dependence on training data and improve the generalization and scalability of model.
Jin Si, Chenxuan Xie, Jiajun Zhou 0003, Shanqing Yu, Lina Chen, Qi Xuan 0001, Chunyu Miao
Mob. Networks Appl.1
2024 FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning
abstract
Recently, sparse tensor algebra (SpTA) plays an increasingly important role in machine learning. However, due to the unstructured sparsity of SpTA, the general-purpose processors (e.g., GPU and CPU) are inefficient because of the underutilized hardware resources. Sparse kernel accelerators are optimized for specific tasks. However, their dedicated processing units and data paths cannot effectively support other SpTA tasks with different dataflow and various sparsity, resulting in performance degradation. This paper proposes FEASTA, a Flexible and Efficient Accelerator for Sparse Tensor Algebra. To process general SpTA tasks with various sparsity efficiently, we design FEASTA meticulously from three levels. At the dataflow abstraction level, we apply the Einstein Summation on the sparse fiber tree data structure to model the unified execution flow of general SpTA as joining and merging the fiber tree. At the instruction set architecture (ISA) level, a general SpTA ISA is proposed based on the execution flow. It includes different types of instructions for dense and sparse data, achieving flexibility and efficiency at the instruction level. At the architecture level, an instruction-driven architecture consisting of configurable and high-performance function units is designed, supporting the flexible and efficient ISA. Evaluations show that FEASTA has 5.40× geomean energy efficiency improvements compared to GPU among various workloads. FEASTA delivers 1.47× and 3.19× higher performance on sparse matrix multiplication kernels compared to state-of-the-art sparse matrix accelerator and CPU extension. Across diverse kernels, FEASTA achieves 1.69-12.70× energy efficiency over existing architectures.
Kai Zhong 0007, Zhenhua Zhu 0002, Guohao Dai 0001, Jin Si, Qiuli Mao, Shulin Zeng, Ke Hong, Genghan Zhang, Huazhong Yang, Yu Wang 0002
ASPLOS (3)7