Julio Pons

dblp:269/8262 · also Julio Pons Terol · DBLP profile ↗
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9ranked-venue papers
0as first author
5since 2021 · last 2024
0000-0002-5654-6753ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 4 since 2021Artificial intelligence and machine learning · 1
YearPublicationVenuePosition
2024 A modular approach to build a hardware testbed for cloud resource management research
Lucia Pons, Salvador Petit, Julio Pons, María Engracia Gómez, Julio Sahuquillo
J. Supercomput.3
2023 Stratus: A Hardware/Software Infrastructure for Controlled Cloud Research
abstract
Cloud systems deploy a wide variety of shared resources and host a large number of tenant applications. To perform cloud research, a small experimental platform is commonly used, which hides the huge system complexity and provides flexibility. Despite being simpler, this platform should include the main cloud system components (hardware and software) to provide representative results. A wide set of platforms have spread in recent years; however, most of them only include a major cloud component or lack the deployment of virtual machines (VMs) to provide isolation. This paper presents Stratus, an experimental platform that is currently being used to carry out cloud research. To the best of our knowledge, Stratus is the only platform that jointly provides three main features: uses VMs to isolate tenant applications, deploys the three types of cloud nodes (server, client, and storage), and manages all main shared system resources (CPUs, LLC space, memory, network, and disk bandwidth). Moreover, Stratus implements a software manager to ease the research and aid the design of QoS-aware policies. The manager integrates three main functionalities: management and control of the execution of VMs and running applications, monitoring of hardware performance counters and system resource utilization, and partitioning of the main shared system resources by using technologies available in commercial processors.
Lucia Pons, Salvador Petit, Julio Pons, María Engracia Gómez, Chaoyi Huang, Julio Sahuquillo
PDP3
2023 Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud
abstract
The increasing popularity of cloud computing has forced cloud providers to build economies of scale to meet the growing demand. Nowadays, data-centers include thousands of physical machines, each hosting many virtual machines (VMs), which share the main system resources, causing interference that can significantly impact on performance. Frequently, these data-centers run latency-critical workloads, whose performance is determined by tail latency, which is very sensitive to the interference of co-running workloads. To prevent QoS violations, cloud providers adopt overprovisioning strategies but they reduce the server utilization and increase the costs. A mechanism that accurately estimates performance degradation dynamically in a production system would allow cloud providers to improve the servers’ utilization. In this work we propose Cloud White, an approach that is able to detect the inter-VM interference in scenarios with multiple co-located latency-critical VMs and estimate the performance degradation using multi-variable regression models. Unlike previous proposals, Cloud White is built taking into account the limitations of a public cloud production system. Experimental results show that Cloud White is able to estimate performance degradation with a small overall prediction error of 5%.
Lucia Pons, Josué Feliu, Julio Sahuquillo, María Engracia Gómez, Salvador Petit, Julio Pons, Chaoyi Huang
Future Gener. Comput. Syst.6
2022 Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning
abstract
Current server processors have redistributed the cache hierarchy space over previous generations. The private L2 cache has been made larger and the shared last level caches (LLC) smaller but designed as non-inclusive to reduce the number of replicated blocks. As a result, the new organization shrinks the per-core cache area.
Lucia Pons, Julio Sahuquillo, Salvador Petit, Julio Pons
ICPP4
2022 Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources
abstract
Multithreaded latency-critical applications represent an important subset of workloads running on public cloud systems. Most of these systems deploy powerful computing servers including Intel Hyper-Threading processors. Understanding how performance is affected by the consumption of the main system resources is a major concern for cloud providers in order to devise virtualization strategies that improve the system efficiency. With this aim, this paper first characterizes the impact of QPS on tail latency, analyzing different scenarios varying the number of threads and the thread-to-core allocation (single-task and multi-task execution) policy. The characterization study reveals that the performance of some applications does not scale with the number of threads, and the performance of some others is insensitive to the Hyper-Threading technology, so they can be allocated in less physical cores and improve system utilization. Identifying these applications, however, at run-time is challenging. Despite identifying these applications at run-time is challenging, this paper shows that they can be successfully detected at run-time by analyzing the utilization trend of the major system resources. In addition to CPU, we have also studied how assigning the share of each application of other major shared system resources impacts on performance. We outline considerations cloud providers should take into account to improve performance and resource utilization.
Lucia Pons, Josué Feliu, José Puche, Chaoyi Huang, Salvador Petit, Julio Pons, María Engracia Gómez, Julio Sahuquillo
Future Gener. Comput. Syst.6
2020 Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance
abstract
The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, however, can lead the system to undesired situations regarding performance and fairness. Recent approaches have successfully addressed fairness and turnaround time (TT) in commercial processors. Nevertheless, these approaches must face sustaining system performance, which is challenging. This work makes two main contributions. LLC behaviors regarding cache performance, data reuse and cache occupancy, that adversely impact on the final performance are identified. Second, based on these behaviors, we propose the Critical-Phase Aware Partitioning Approach (CPA), which reduces TT while sustaining (and even improving) IPC by making an effective use of the LLC space. Experimental results show that CPA outperforms CA, Dunn and KPart state-of-the-art approaches, and improves TT (over 40 percent in some workloads) over Linux default behavior while sustaining or even improving IPC by more than 3 percent in several mixes.
Lucia Pons, Julio Sahuquillo, Vicent Selfa, Salvador Petit, Julio Pons
IEEE Trans. Parallel Distributed Syst.5
2018 Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications
Lucia Pons, Vicent Selfa, Julio Sahuquillo, Salvador Petit, Julio Pons
Euro-Par5
2015 A Multiagent System Proposal for 30 Day Readmission Problem Management
Miguel A. Mateo Pla, Lenin Lemus, José Miguel Montañana, Julio Pons, Salvador Tortajada
KES-AMSTA4
2001 Gigabit Ethernet Backbones with Active Loops
abstract
The current standard Ethernet switches are based on the Spanning Tree (ST) protocol. Their most important restriction is that they can not work when the topology has active loops. In fact, the ST protocol selects a tree from the real topology by blocking the links that are not involved in the tree. This restriction produces a network traffic unbalancing behavior saturating those link near the root switch while rest of links will be idle or with a very low utilization. This paper proposes a new transparent switch protocol for Gigabit Ethernet backbones that considerably improves the performance of current ones. The proposed protocol is named ALOR for Active Loops and Optimal Routing. ALOR protocol could be used in the last stage of a fat tree network in order to allow a final backbone with active loops. So, rings, mesh and other regular/irregular active loop topologies can be used to connect the Gigabit switches in order to obtain better performance results.
Román García, Manuel P. Malumbres, Julio Pons
ICPP3