Demo Data from EDBT 2026 / reviewers in the wild / expert
Sourasis Das
dblp:27/10937
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Requirements engineering and software design · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault analysis |
0.1 | 1 | 2012 | Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation
hardware verification and test |
0.1 | 1 | 2012 | Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Electronic design automation › hardware verification and test
test generation |
0.1 | 1 | 2012 | Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Requirements engineering and software design
formal specification |
0.0 | 1 | 2012 | Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012 |
Methods — techniques the papers use, named apart from their topics
formal specification-based test generation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | A Generalized Theory for Formal Assertion CoverageabstractCoverage of formal property specifications has important ramifications in design verification. Mutation coverage, a well studied approach towards specification coverage, checks whether the specification fails in the presence of a fault. Existing mutation coverage methods are broadly divided into those which inject the fault into a given implementation and those which inject the fault directly into the specification. This paper presents a theory which unifies these contrasting approaches and extends the mutation coverage approach to partial implementations where some components are given, and for the others, we only have component specifications. Sourasis Das, Ansuman Banerjee, Pallab Dasgupta |
Asian Test Symposium | 1 |
| 2012 | Early Analysis of Critical Faults: An Approach to Test Generation From Formal SpecificationsabstractThis paper presents a formal methodology for test generation from formal specifications. Our method can be used for test generation for critical faults in component-based designs. Test generation for critical faults is done entirely using formal specifications and therefore the theory inherently guarantees that a generated test will be applicable to any implementation of the specifications. The theory makes fault analysis possible at an abstract level of design where the complete logic is not specified. Sourasis Das, Ansuman Banerjee, Pallab Dasgupta |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |