Bio-inspired axonal and dendritic delay-based spiking neural network algorithms perform spatiotemporal pattern recognition efficiently within feed-forward networks, making complex and suboptimal recurrent neural network structures unnecessary. Including trainable dendritic or axonal delays in feed-forward neural networks reduces neural network complexity and improves classification performance significantly. However, generating tunable low-power hardware spike delays of the biological timescale (few μs to ms ) without adding an extra penalty on the area has been challenging over the years. We present a novel band-to-band tunneling-based tunable delay element for spiking neural network hardware. The proposed low-power core delay element capable of providing spike delays of up to 0.4 ms (without explicit capacitance) consumes an area of 50 μm2in GF45RFSOI technology with a peak power of 320 nW, which is the lowest among state-of-the-art spike delay generation circuits. Moreover, the order of the spike delay can be extended to 25 ms by adding an explicit on-chip capacitance of 500 fF.

Combinatorial optimization problems (COPs), when addressed using traditional von Neumann computers, demand significant computational power and substantial area as problem dimensionality increases. Hardware-based solvers, particularly those employing coupled oscillator networks to mimic Ising machines, have been explored as alternatives. However, conventional CMOS-based solutions face limitations in terms of power consumption and area. In this work, we propose a low-power 8-node oscillatory neural network using a band-to-band-tunneling-based ring oscillator in GF45RFSOI technology. This ultra-low power and low-area design efficiently solves COPs without an external perturbation signal. We use the intrinsic noise of BTBT-based oscillators to augment the phase synchronization among the coupled oscillators. The proposed system allows configurable all-to-all connectivity between ring oscillator nodes through cross-coupled capacitors. We demonstrate the system’s efficacy in solving multiple vector graph coloring problems, achieving an average power consumption of 0.93 nW (105× lower than state-of-the-art) per oscillator with a supply voltage of 1.8 V.

On-chip training at the edge becomes a primary requisite for real-time and security-sensitive artificial neural network (ANN) applications. In-memory computation (IMC) techniques have been proposed to facilitate data-intensive computational operations in ANNs. IMC-based multiply-accumulate (MAC) accelerates ANN training but suffers from significant communication overhead between the MAC engine and the off-chip storage for the intermediate data. This article proposes an analog temporary on-chip memory (ATOM) to store this intermediate data during ANN training. The ANN training architecture with the proposed ATOM has two significant advantages. First, the energy required to store intermediate data is scaled down by \(\sim\) 40 \(\times\) due to the on-chip and analog nature of the memory. Second, the proposed architecture avoids power and area-consuming analog-to-digital converters (ADCs) between neural network stages. The ATOM cell measurements are carried out from 20 fabricated chips, and the impact of ATOM characteristics on ANN system performance accuracy is analyzed. This article shows significant latency improvement of \(\sim\) 9 \(\times\) and area savings of \(\sim\) 5 \(\times\) for intermediate data storage compared to the on-chip SRAM during ANN training’s forward and backward pass operations. An improvement in the area and latency will be beneficial to instrument the area- and energy-efficient hardware system for on-chip ANN applications.

Analog in-memory computing (IMC) techniques have played a significant role in vastly improving the throughput, energy efficiency, and area of on-chip ML inference engines, breaking through the Von-Neumann memory bottleneck. However, the innate susceptibility to process, voltage and temperature (PVT) variations in effect restricts analog computing to ML inference applications of low to moderate complexity. In this work, we present a novel PVT variation tolerant SRAM based temporary memory (STEM) for analog in-memory computing. The proposed technique also allows unit cells to operate at ultralow currents, thereby enabling better energy efficiency. Monte Carlo simulations show that the proposed temporary memory array achieves a unit cell current variability (σ/μ) of 2% which is 5× better than that of conventional 8T unit cell. System level simulations of a 64 × 64 macro show that the proposed STEM achieves near baseline classification accuracy on FMNIST dataset using pre-trained weights, without chip-specific training.

Efficient and compact neurons with low power consumption are crucial when designing large-scale spiking neural networks (SNNs) for hardware implementation. Many architectures in the literature showcase different spike patterns associated with biological neurons. However, using bulky capacitors to generate the different time constants related to complex neuron patterns makes these circuits area inefficient. This paper presents a band-to-band-tunneling (BTBT) based energy-efficient and compact neuron capable of producing various spike patterns. The BTBT region’s extremely low current enables different time constants while eliminating the need of bulky capacitors. The circuit is based on the Izhikevich neuron model. The proposed circuit is designed in Silicon on Insulator technology to exhibit important firing patterns observed in the biological cortex, viz. regular spiking, fast-spiking, and chattering, and it is fine-tuned for efficient operation at low subthreshold voltages. This circuit utilizes only 129 μm2area and consumes only 6.7 fJ energy per spike ( approximately 40% lower area and energy per spike than state-of-the-art multi-mode neurons) in G45RFSOI technology.

Solving classification problems using Spiking Neural Networks (SNNs) involves determining the most active neuron in the output layer. Scalable, low-power and low-area hardware solutions for such decision-making are vital for neuromorphic edge applications to meet power and space constraints. In this work, we propose a low-power, compact Winner-Take-All (WTA) circuit, a multi-input multi-output dynamic threshold comparator that simultaneously compares multiple analog voltage inputs and provides a one-hot-encoded digital output vector indicating the result of the classification. The design eliminates the need for cascading and a dedicated feedback circuit. A spike integrator stage captures the temporal activity of a set of neurons, and these activities are compared and digitized by the proposed WTA comparator stage. The proposed WTA designed in GF45RFSOI technology, exhibits self-excitation and global-inhibition properties, offers scalability, consumes 44% less power (140 nW ) and occupies a 40% lower area (166 μm2), compared to state-of-the-art.

This work presents a continuous-time delta-sigma modulator (CTDSM) deploying an experimentally demonstrated band-to-band-tunelling (BTBT) SOI MOSFET-based loop filter. With a compact, low-pass filter circuit and extremely low current in the BTBT regime, a loop filter implementation will provide optimality in terms of area and power performance. In literature for moderate-resolution CTDSMs, traditional loop filters are implemented with either fully passive, active, or hybrid integrators. These designs have a tight tradeoff in terms of area and power. The passive integrators have optimal power but suboptimal area, while the active integrators have optimal area and sub-optimal power consumption. The proposed work tries to break this tradeoff using BTBT regime loop filters. The CTDSM was designed in a GF45RFSOI technology and achieves a peak SNR/SNDR of 48.41 dB/47.94 dB for a 5 kHz bandwidth. The power consumption is 76.3 nW, with an area of 102.7 μm2— more than 100x area reduction over previous state-of-the-art moderate-precision CTDSM designs. This makes the proposed CTDSM extremely compact and power-efficient compared to traditional state-of-the-art moderate-resolution DSMs.

Metal-insulator–metal (MIM) capacitors are inevitable and critical passive components in analog, mixed-signal, and memory applications. These capacitors occupy nearly 40% of circuit area among other passive and active components of the integrated circuit (IC). Considering this fact, the International Roadmap for Devices and Systems (IRDS) recognized and recommended the miniaturization of MIM capacitors with high permittivity dielectric materials. For future analog and radio frequency (RF) applications, the IRDS has predicted that MIM capacitors should hold a high capacitance density of$\gt {10}~\text {fF}/\mu \text {m}^{{2}}$, a low voltage linearity of$\lt {100}~\text {ppm}/\text {V}^{{2}}$, and a low leakage current density of$\lt {10}~\text {nA}/\text {cm}^{{2}}$. In this regard, many research works have been carried out over the last few decades with various high-k dielectrics to achieve “low voltage linearity.” However, many of them are facing problems with structural defects, interface traps, and poor polarization process due to limitations of fabrication processes. This article attempts to review the challenges and opportunities involved in the reduction of voltage linearity and leakage of MIM capacitors. Also, this article presents the physical limits and challenges involved in MIM capacitor integration with back end of line (BEOL) process of recent complementary metal-oxide–semiconductor (CMOS) technologies. Using physical modeling, the design formula for low voltage linearity coefficient was derived, which helps IC developers in the design and implementation of highly linear RF-analog and mixed-signal (AMS) systems.

Liquid State Machine (LSM) is a brain-inspired neural network architecture for solving temporal classification problems like speech recognition. The simple structure of LSM with a reservoir and single-layer classifier is attractive from a hardware implementation perspective. When the LSM is considered for low-power hardware implementation in real-world command word recognition tasks, challenges like nonidealities in sensor filter response and ambient noise become critical concerns. In this work, we evaluate the performance of LSM based on two aspects (1) ambient noise and (2) sensor/preprocessing circuit nonidealities. For Ambient noise, we use additive white gaussian noise (AWGN) and ambient noise using the iNoise Indian Noise dataset that covers various natural indoor, outdoor, and travel-related environmental sounds. To understand the impact of input hardware nonidealities, we analyzed the impact of the audio preprocessing filter's quality factor, order, center frequency variations, and output nonlinearity on LSM performance. We use the spoken digits classification in the TI-46 dataset. This paper's findings present design guidelines for the system designers intending to use liquid-state machines for speech classification tasks. In terms of filter design, first, there is a broad Q, order space for filter design where performance is high. We use the hardware-friendly parallel 4th order Butterworth bandpass filter model to provide a baseline 98% accuracy in speech classification tasks. Second, the performance of LSM degrades proportionally to the variation in the center frequency of the bandpass filters in the filter bank. Third, nonlinearity with the third-order harmonic of 50 dBc can be tolerated. Regarding ambient noise, our study shows that a 40 dB SNR for AWGN is sufficient for ideal performance. Second, the best case of “home” noise leads to a performance of 91.4%. Outdoor and travel noise reduce the classification performance to 78.8% and 62.4%, respectively. However, ideal performance is recovered if the signal to noise ratio (SNR) is increased, particularly by 10 dB in indoor conditions and 30 dB in outdoor conditions. Thus, our study presents an engineering evaluation for real-world spoken digit recognition using LSMs.

Resistive RAM (RRAM) devices are compact and easy to fabricate with electrical inputs-based switching. Conductive-Bridge RRAM (CBRAM) is being developed to meet retention, endurance and reliability specifications by GlobalFoundries for typical 1-bit per cell digital storage. However, filamentary growth and rupture produce variability, and the resistance states can often span multiple orders. We explore whether digital-storage-focused CBRAM can support analog current readout-based Multiply-and-Accumulate operations in artificial neural network (ANN) applications. We explore the 2T-1R bit cell to tune the mean HRS/LRS ratio and to control the variability in HRS and LRS readouts. We use experimental CBRAM data and GlobalFoundries' 22FDX platform and demonstrate > 2 × reduction in HRS and LRS logscale variability and > 10 × higher HRS/LRS ratio for the 2T-1R bit cell. The strategy is successfully tested for two datasets – the simpler MNIST and the more complex FMNIST using system-level modeling of non-idealities like weight quantization, HRS/LRS ratio, and variability in the readout of each bit-cell. Such bit-cell design principles have general utility in exploiting variability-prone characteristics of emerging memories for excellent application-level performance.

Recently, diamond color defect based quantum sensing applications such as nitrogen-vacancy (NV) center magnetometry have emerged in CMOS technology, which use optically detected magnetic resonance (ODMR) for sensing magnetic field strengths $(|\tilde{\mathrm{B}}|)$ from different environmental physical quantities. For ODMR based sensing, CMOS quantum sensors seek an onchip 2.87 GHz microwave (MW) signal generator. Moreover, in order to sense smaller $|\tilde{\mathrm{B}}|$, these CMOS quantum sensors also require that MW signal should be swept with sufficiently small step-size near 2.87 GHz. In this work, we present a fractional-N synthesizer based 2.87 GHz MW-generator (MWG) with an extremely small programmable sweep step-size for improved sensitivity of $|\tilde{\mathrm{B}}|$ measurements in CMOS NV magnetometry. The proposed MWG is implemented in 180 nm CMOS technology and simulations were done to validate the proposed design. Post-layout simulation results show that the proposed MWG achieves a minimum sweep-step size of 50 kHz, which can be used to sense $|\tilde{\mathrm{B}}|\lt 0.9\;\mu \mathrm{T}$ and exhibits a phase noise of −114.5 dBc/Hz at an offset of 1 MHz near 2.87 GHz center frequency.

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of recurrent SNN using proposed low-power, low-area, and low-leakage band-to-band-tunneling (BTBT) based neurons. A low-power thresholding circuit is proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. The tunneling regime enables a high input impedance in the BTBT neurons (few$\text{G}\Omega$) to enable a voltage input without loading the synaptic array. To verify the effect of the proposed neuron, a 36-neuron recurrent SNN is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.

The design of$\Delta \Sigma $modulators for multichannel biomedical applications introduces challenges with high density and very low power consumption. While possible solutions in the form of VCO and passive integrator-based$\Delta \Sigma $modulators have been reported, these modulators suffer from limited resolution. Hybrid$\Delta \Sigma $modulators provide an excellent tradeoff between area, power, and achievable resolution compared to the counterpart active and passive integrator$\Delta \Sigma $modulators. This work explores hybrid continuous-time delta–sigma modulator (CTDSM) architectures for multichannel biomedical applications, operating with a single clock phase. To alleviate the high power consumption of the active integrators in the CTDSM, an auxiliary digital-to-analog converter (DAC)-based and a passive$RC$front-end-based hybrid CTDSMs are proposed. Through a detailed analysis and performance comparison, we demonstrate that the two proposed hybrid architectures exhibit the classical area–power tradeoff for a target resolution. We demonstrate the designs in standard 180-nm mixed-mode CMOS technology for biomedical bandwidth. Measurement results show that the auxiliary DAC and the PRC-FE-based hybrid CTDSMs achieve an SNDR and DR of 65.18 and 68.3 dB and 66.85 and 71.1 dB while consuming 845- and 730-nW power and achieving an FoM of 28.48 and 20.3 fJ/conv, respectively, ideal for multichannel biomedical applications.In vitroandin vivomeasurements are also performed to validate the proposed hybrid CTDSM designs.

Resonant MEMS sensors have potential of providing highly precise measurements. The accurate processing of the output relies on precise frequency estimation techniques especially in the context of portable sensors for particulate matter. This paper investigates five commonly used single-tone frequency estimation techniques (3-point DFT interpolation, parabolic interpolation of periodogram peak, Prony's method, modified Pisarenko and zero crossing method) with respect to the estimation accuracy, memory requirement and computational complexity. The effect of noise and harmonics on estimation accuracy of these five techniques are analyzed and validated through simulation. The experimental data is acquired from a resonant MEMS sensor with a center frequency of 3.15 MHz. The output is sampled at 100MS/s using a 12-bit ADC. These five techniques are applied to the various data sets acquired from an experimental setup. The comparison results along with the analysis are presented.

In this paper, a new look-up table (LUT) method is proposed to reduce the simulation time and the run time memory requirement for large logic and mixed signal simulations. In the proposed method, for the first time, circuit with multiple devices is replaced by one LUT model, called circuit LUT. The replacement results in significant reduction of the run time memory requirement. The replacement also reduces the number of interpolation steps to be performed at every Newton-Raphson iteration during the simulation that results in significant reduction of simulation time. With the proposed method, the simulation speed is improved by two times over the conventional LUT models developed for devices. In addition, 25% reduction in the run time memory requirement is also achieved by the proposed method.

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time ΔΣ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement results show that the CTDSM achieves a peak SNDR of 54.81 dB and DR of 57.4 dB while consuming a core power of 1.76 μW at 300-mV supply voltage without the clock-gated comparator. With the clock-gated auto shutdown comparator, the CTDSM consumes a core power of only 220 nW thereby providing an eight times power saving. Moreover, the fabricated CTDSM occupies an extremely small area of 0.0464 mm2 with an energy efficiency of 24.5 fJ/conv making it the most compact and energy-efficient CTDSM reported till date among the moderate resolution CTDSMs. Furthermore, by increasing the supply voltage to 400 mV, the CTDSM features a peak SNDR of 58.56 dB and DR of 64.1 dB while consuming a core power of 410 nW and 29.61 fJ/conv.

This paper presents a novel power management circuit (PMC) for harvesting the energy from the ambient. The proposed PMC comprises an energy harvester, a startup, a dc–dc boost converter, and a dc–dc buck converter. The PMC is capable of working with various low-power energy harvesters and can track the maximum power point after every 4.5 s. To achieve the maximum power point tracking (MPPT), an open-circuit-voltage-based method is used to transfer the maximum power from the energy harvester to the power optimized boost converter. The proposed MPPT scheme works for a wide range of equivalent source resistance of the energy harvester in the range of$20~\Omega $–1$\text{M}\Omega $. An auxiliary energy harvester is used for the startup to avoid any external supply. Regulated voltage across a load is provided by the buck converter which features sharing the switches and inductor with the boost converter. The complete circuit is designed, optimized, and simulated in 180-nm mixed-mode CMOS technology using three different types of energy harvesters, which are precisely characterized and modeled. Post-layout simulated results are presented for the input power ranging from 150 nW to$500~\mu \text{W}$for different values of source resistances ranging from$20~\Omega $to 1$\text{M}\Omega $. For a source resistance of 100$\text{k}\Omega $, the efficiency of the boost converter is 39.91% and 89.91% at available power of 156 nW and 2.5$\mu \text{W}$, respectively. The buck converter is able to regulate the load voltage to 1 V across the load resistance ranging from$100~\Omega $to 2$\text{k}\Omega $.

This paper presents a low-power integrated wireless telemetry system (Bio-WiTel) for healthcare applications in 401-406 MHz frequency band of medical device radiocommunication (MedRadio) spectrum. In this paper, necessary design considerations for telemetry system for short-range (upto 3 m) communication of biosignals are presented. These considerations help greatly in making important design decisions, which eventually lead to a simple, low power, robust, and reliable wireless system implementation. Transmitter (TX) and receiver (RX) of Bio-WiTel system have been fabricated in 180 nm mixed mode CMOS technology. While radiating -18 dBm output power to a 50 antenna, the packaged TX IC consumes 250 μW power in 100% on state from 1 V supply, whereas the RX IC consumes 990 μW power from 1.8 V supply with a sensitivity of -75 dBm. Measurement results show that TX fulfils the spectral mask requirement at a maximum data rate of 72 kb/s. The measured bit error rate (BER) of RX is less than for a data rate of 200 kb/s. The proposed Bio-WiTel system is tested successfully in home and hospital environments for the communication of electrocardiogram and photoplethysmogram signals at a data rate of 57.6 kb/s with a measured BER of <10 for a maximum distance of 3 m.

In this paper, we are presenting a novel programmable gain and bandwidth instrumentation amplifier (PGB-INA) for biomedical applications. By virtue of its programmable gain and bandwidth, it can measure various bio-potentials such as ECG, EMG, EOG, etc. The proposed PGB-INA also features an extremely low input referred noise (1.34 μVrms within the integration bandwidth of 50 mHz to 11 kHz) and high CMRR (84 dB). The design is fabricated in 180 nm mixed-mode CMOS technology. The PgB-INA provides a measured programmable gain and bandwidth of 30 to 40 dB and 100 Hz to 2.7 kHz, respectively. The PGB-INA occupies die area of only 150 μm × 200 μm and consumes 18.3 μΑ current from 1.8 V supply. Various bio-potentials are measured using the proposed PGB-INA such as ECG, EMG and EOG which are also presented in the paper.

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed configurations provide a more relaxed tradeoff between SER and other specifications mainly delay, power dissipation and area. RTL implementation of a proposed latch is also shown to verify the behaviour subjected to the transient faults. The benefit of implementing a SE tolerant circuit in VHDL language is the feasibility to exhaustively check the immunity of the circuit against transient faults at every sensitive node by just writing simple boolean expressions of each element in the circuit. The proposed configurations and a few selected reported configurations have been also designed, laid out and post layout extracted in 90 nm CMOS logic technology. Post layout simulations have been performed on all proposed latch configurations with clock frequency of 500 MHz and performance comparison results are presented.

A novel receiver front-end is proposed for FM/FSK modulated signal, which is transmitted from a body worn device in the MedRadio spectrum of 401–406 MHz. The front-end comprises a low noise amplifier (LNA), a zero crossing detector (ZCD) and a frequency to digital converter (FDC). The proposed architecture offers direct digitization of the input signal and is immune to LO leakage and problem of image frequencies. Designed in 180 nm mixed mode CMOS technology, the worst case post layout simulation results show a sensitivity of −80 dBm at 200 kbps for FSK modulated input with only 990 μW power consumption.

This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by ±3.4% across 18 fabricated chips and over temperatures ranging from 25 °C to 100 °C. Simulations show that variation of the transconductance across process corners is ±6.7% and across temperature range of 0 °C to 100 °C is ±1.6%. The proposed PT-invariant transconductor has the minimum variation among the fully on-chip transconductors reported so far. The proposed circuit consumes 136 μW of power.

Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.

A novel first order ultra low power and area efficient band-pass Gm-C filter aimed for varieties of neuro-potential signal conditioning applications, in 180nm CMOS process, is presented. The proposed Gm-C filter takes advantage of an ultra low-power constant Gm/C circuit, which leads to constant gain and bandwidth performance. Total current consumption of the bandpass Gm-C filter is 4.03μA and operates at 1.8V supply voltage. The proposed filter has a tunable bandwidth from 160Hz to 7.2kHz and exhibits input referred noise voltage of 4.17μV for a bandwidth of 10.2kHz. The filter provides output voltage swing of 1.55V and occupies area of 250μm x 250μm.

An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis shows that energy dissipation per bit can be reduced to the minimum possible normalized level, which is approximately 200 times lower than reported theoretical values. Simulation results of the proposed DAC in 90nm UMC MM CMOS process are also presented.

This paper presents a current-mode signalling scheme for bidirectional long on-chip interconnects. The transceiver has been fabricated in 180nm CMOS process. Features of the proposed scheme are driver pre-emphasis and low impedance termination. While no extra repeater is needed for line lengths up to 8mm long the scheme improves the delay by 34% for 2mm-8mm long lines, compared to bidirectional voltage-mode links. The scheme also improves the power performance for line lengths longer than 2mm, operating at data rates higher than 180Mbps. Measurement results show that delay and power-delay product improve by 18% and 3.7x, respectively, compared to simulation results of the voltage-mode scheme.

This paper presents a novel table-based approach for efficient statistical analysis of Finfield effect transistor circuits. The proposed approach uses a new scheme for interpolation of look-up tables (LUTs) with respect to process parameters. The effect of various process parameters, viz., channel length, fin width, and effective oxide thickness is studied for three circuits: buffer chain, static random access memory cell, and high-gain low-voltage op-amp. Compared to mixed-mode (device-circuit) simulation, the proposed LUT-based approach is shown to be much faster, thus making it practically a feasible and attractive option for variability analysis especially for emerging technologies where compact models are not available for circuit simulation.

In the paper “An analog 2-D DCT processor,” authors have presented a row-column method for computing 2-D discrete cosine transform (DCT). They have reported minimum peak signal-to-noise ratios (PSNR) 40.6 dB and 31.4 dB for 4-point and 8-point DCT, respectively. The main objective of this comment letter is to point out that those PSNR values are not correctly calculated. The actual minimum PSNR values are shown to be 24.7 dB and 22.7 dB for 4-point and 8-point DCT, respectively. Similarly, maximum PSNR values are corrected in this letter.

Recently a new CMOS current-mode pseudo-exponential function generator circuit was reported by Popa. The entire analysis and exponential function generator circuit, given in Popa's paper, is based on a current-squaring circuit module. In this comment paper we show that the current-squarer circuit, presented in Popa's paper, does not work as a current squarer. Consequently the pseudo-exponential generator also does not work as described in Popa's paper. We present a detailed mathematical analysis in this paper to derive its actual operation. Simulation results of the circuit module using Mentor Graphics custom IC design tool set, in a TSMC 0.18-μm CMOS process, are also shown in this paper. Simulation results match the behavior predicted by mathematical analysis.

A novel table-based environment for automatic design and optimization of FinFET circuits is demonstrated. A new accurate look-up table (LUT) technique is implemented in a circuit simulator and integrated with particle swarm optimization algorithm for efficient circuit designs in novel devices. Op-amp circuits are designed and optimized to demonstrate the accuracy and usefulness of the proposed platform. Further, it is shown that the proposed design methodology can take into account variations in process, supply voltage, and temperature.

Current mode signaling(CMS) scheme is one of the promising alternatives to voltage mode buffer insertion scheme for high-speed low-power data transmission over long on-chip interconnects. In this paper we present a CMS scheme with dynamic overdriving driver (DOD) whose performance is robust against intra-die and inter-die process variations. We show that throughput of the CMS scheme proposed in [1] degrades by 33% in the presence of intra-die process variations whereas that of the scheme in [2] degrades by 36% in the worst case process corner. Simulation results show that throughput of the proposed CMS scheme degrades by only 9.5% in presence of intra-die process variations and 22% in the worst case process corner. In this process corner, logic speed itself degrades by 23% and hence 22% of throughput degradation of the proposed signaling scheme is not a major concern. In the typical process corner, the proposed CMS scheme shows 14% and 19% improvement in delay and power, respectively over CMS scheme proposed in [1].

A new lookup-table (LUT) approach, based on normalization of the drain current with anID-VGtemplate, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.

In this paper we show that current mode signaling system with receivers using inductive input impedance can provide a low power solution to high speed data transmission over long lines. We show that beta multiplier circuits can be designed such that they exhibit inductive input impedance and their use as current mode receivers provides significant enhancement in data rates. Simulation results show that it is possible to transmit data at eight times higher data rates than voltage mode with an one order of magnitude lower power consumption. Even compared to other current mode signaling systems, those using receiver with inductive input impedance show around 50% improvement in data rate at marginally lower power consumption.