In this paper we present a 4.5-track standard cell library using ASAP7 PDK extended to support buried-power rails and backside metal wires for power distribution. This work showcases a successful implementation of a 4.5-track cell library by a co-optimization performed at process, cell, and chip levels. Experimental results show that the 4.5-track cell library can improve the ratio of timing performance to area and the ratio of timing performance to power dissipation by 43% and 27% respectively when compared with the results obtained with a six-track cell library.

On-grid pin access is necessary for 1-D regular layout design. It is also instrumental to detailed routing efficiency. As semiconductor technology advances, on-grid pin access becomes a distant goal due to increasing discrepancy between contacted polysilicon pitch (CPP) and M1 pitch (M1P). Though the multiple-layout approach to this problem was proposed for some specific case, no investigation into its impact on chip-level routing is found. In this paper, we generalize the multiple-layout approach. We design a 7.5-track standard cell library for the case of the ratio CPP/MIP = 3/2 to study the impact of the multiple-layout approach on chip-level routing. The experiments for this specific case show that the multiple-layout approach can achieve not only on-grid pin accesses but also 46% to 83% fewer DRC violations with 28% to 50% less runtime at the expense of 5% to 13% increase in the longest path delay. If on-grid pin access is a must, the increase in the longest path delay is the price for fulfilling such a requirement.

Owing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches for the multilayer obstacle-avoiding rectilinear Steiner tree (ML-OARST) problem are thus nonmaze routing-based approaches for runtime issues, yet they cannot be directly applied to deal with additional constraints such as variant edge weights on a routing layer. In this article, we propose the maze routing-based methodology with bounded exploration and path-assessed retracing to reduce runtime and routing cost for the constrained ML-OARST construction problem. The exploration of maze routing is bounded to reduce the runtime; the costs of connecting pins are computed to select Steiner points in the retracing phase. To further reduce the routing cost, we develop a Steiner point-based ripping-up and rebuilding scheme for altering tree topology. Experimental results on industrial and randomly generated benchmarks demonstrate that the proposed methodology can provide a solution with good quality in terms of routing cost and has a significant speedup compared to traditional maze routing. A commercial tool is also used to show the effectiveness of the proposed methodology.

The benefits of applying maze routing algorithm over non-maze routing based methods include the feasibility of imposing various additional constraints on routing graphs. However, the much higher complexity of a multi-layer routing graph than that of a single-layer routing graph significantly increases the required runtime of conducting maze routing to solve the multi-layer obstacle-avoiding rectilinear Steiner tree (ML-OARST) problem, making applying maze routing to this problem infeasible. In this paper, we present a maze routing-based algorithm with the proposed Steiner point pre-selection to guide the construction of a ML-OARST. This can achieve a favorable balance between quality and runtime. The quality of routing is determined by total cost, that is, the summation of wire-length and via cost. To improve the flexibility of routing tree generation, we also propose a rip-up and re-building strategy for altering Steiner points and tree topology. Compared with a multi-layer multi-terminal maze routing algorithm, our algorithm can reduce the total cost by 4.8% on average and achieve 45x runtime speed-up averagely; moreover, our algorithm outperforms the state-of-the-art ML-OARST method using computational geometry techniques in terms of wire-length. With additional costs on routing graph, the proposed maze routing-based method can be further enhanced to solve VLSI routing constraints, such as layer-specific costs, scenic control, and layer directive.

The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition. We hope that the contest evaluation frameworks and benchmarks boost research on these critical problems and help EDA community discover novel, efficient, high-quality solutions to advance the state-of-the-art in EDA.

The CAD Contest at ICCAD is a challenging, multi-month competition, focusing on advanced, real-world problems in the field of Electronic Design Automation (EDA). In its fifth year, the 2016 CAD Contest at ICCAD attracted 135 teams from 11 regions/countries. Three critical EDA problems, in the areas of design verification, logic synthesis, and design for manufacturing (DFM), were called for competition this year. We hope that the contest benchmark suites and evaluation infrastructure boost research in the related areas and help EDA community find novel and high-quality solutions to the problems.

The 2015 CAD Contest at ICCAD presents cutting-edge, real-world EDA problems and challenging benchmarks derived from modern industrial designs. It also provides a standard, publicly available evaluation framework for each of the problems. The ever-increasing complexity of integrated circuit design has brought forth new and challenging problems for the EDA community. These require novel, efficient, and high-quality algorithms and methodologies. It is our hope that the CAD Contest at ICCAD would encourage timely and much-needed research on these critical problems in the field of EDA.

This paper presents a via-configurable logic block and a design methodology for realizing fine-grained dual-supply-voltage structured ASIC. Experiments with a 90nm process technology show that, given various timing budgets, our approach can achieve up to 44% energy reduction with 1.6% area overhead on level converters. Compared with GECVS, our approach converts up to 39% more high-supply voltage gates into low-supply voltage gates.

In this paper we propose a flexible slack budgeting approach for post-placement multi-bit flip-flop (MBFF) merging. Our approach considers existing wiring topology and flip-flop delay changes for achieving more accurate slack budgeting. Besides, we propose a slack-to-length converting approach to translating timing slack into equivalent wire length for simplifying a merging process. We also develop a merging method to evaluate our slack budgeting approach. Our slack budgeting and MBFF merging programs are fully integrated into an industrial design flow. Experimental results show that our approach on average achieves 3.4% area saving, 50% clock tree power saving, and 5.3% total power saving.

This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2|n| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.

A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic gate. We devise four new VCLBs and construct several cell libraries based on these VCLBs. We develop a design flow mostly using industrial design tools and propose a method to evaluate VCLB viability. The experimental results show that a medium-grained VCLB that realizes a rich set of logic functions attains the best performance.

Clock gating is an effective method of reducing power dissipation of a high-performance circuit. However, deployment of gated cells increases the difficulty of optimizing a clock tree. In this paper, we propose a delay-matching approach to addressing this problem. Delay-matching uses gated cells whose timing characteristics are similar to that of their clock buffer (inverter) counterparts. It attains better slew and much smaller latency with comparable clock skew and less area when compared to type-matching. The skew of a delay-matching gated tree, just like the one generated by type-matching, is insensitive to process and operating corner variations. Besides, delay-matching ECO of a gated tree excels in preserving the original timing characteristics of the gated tree.

In this paper we present a router called Rover for structured ASICs with via-configurable routing fabrics. We present a statistical approach to estimating available routing resource of a predefined routing fabric. We also introduce a concept called pseudo Steiner point to enable higher routing flexibility. We integrate Rover into an industrial design flow. Rover can successfully route a design with 280 thousand two-terminal nets in slightly more than an hour. Compared to a commercial yet non-structured ASIC router without a predefined routing fabric, Rover on average incurs a 47% (5%) increase in total wire length (when not counting overhang wire length). It incurs a 32% increase in the longest path delay, which is considerably smaller than a 47% increase in total wire length.

Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a power gated design flow mostly using existing standard cell design tools. We can configure PGVCLBs in a design to implement fine-grained power gating, coarse-grained/cluster-based power gating or even distributed sleep transistor network (DSTN). With fine-grained power gating, we can achieve 52% leakage reduction on average with only 8% area and 17% delay overheads when compared to the data obtained using a non-power-gated library.

In this article we study layout and circuit implementations of 3-input lookup table (3-LUT) for via configurable structured ASIC. We present a new 3-LUT circuit and several layout designs. We also propose a method to improve the delay of any logic function with fewer inputs. A 3-LUT, being able to realize all the 256 3-input functions, enables us to synthesize a circuit using both a standard cell synthesizer and an FPGA technology mapper such as FlowMap. Our study shows that circuits synthesized using a standard-cell synthesizer usually achieves better timing than that obtained by FlowMap. Our study further shows that the well-known 3-LUT implemented with multiplexers achieves better timing, area, and power dissipation. Our methodology can be also employed to study look-up tables with more inputs.

This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS'89 benchmarks.

Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to generate the low power test set. Experimental results show, the two problems, especially in the reduction of testing power, can be significantly improved with limited hardware overhead.

In this paper we propose a synergetic approach that integrates router design and cell library engineering for improving post-routing via1 (via between M1 and M2) doubling rate at pins. We develop a double-via (DV) aware multilevel router to exploit the via1 doubling possibilities provided to the cells in a conventional as well as a DV-driven cell library. Compared to a non-DV-aware router using a conventional cell library, our approach using a DV-driven library can on average raise via1 doubling rate by 34%, raise total via doubling rate by 11%, reduce the total number of vias by 3%, and reduce the total number of via1s by 8%. All this can be achieved without incurring any performance and area penalties.

Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility among chips with large-volume requirements while minimizing reticle dimensions. Our mixed-integer linear programming models with VOCO are too complex to render good solutions for large test cases. Our B*-tree with VOCO and HQ with VOCO use 16%∼ 29% fewer wafers and 8%∼ 19% less reticle area than the hierarchical quadrisection (HQ) method proposed by Kahng et al. [2005]

Multiproject wafer (MPW) production cost is sensitive to how the chips are arranged in a reticle. In this paper, we propose a methodology for exploring the reticle floorplan design space to minimize MPW production cost. Experimental results show that our methodology often achieves double-digit cost savings. A study using MPW for volume production shows that the volume cutoff points range from a few thousand dice to tens of thousands of dice. Note to Practitioners-This paper proposes a methodology for minimizing MPW production cost via better chip placement in a reticle (called reticle floorplanning). Our methodology consists of an effective reticle floorplanning method, two simulated wafer dicing methods, two cost estimation models, and a procedure for calculating the cost assumed by each project. A design service company or a foundry can use our methodology to reduce MPW production cost and, thus, provides a more affordable and expedient service to its customers. The reticle floorplanning method and simulated wafer dicing methods employed here are the state-of-the-art. A practitioner should adapt these methods to other MPW problems such as dealing with multitechnology process, placing multiple instances of the same design in a reticle, etc. The cost models should also be revised accordingly. The cost data given in this paper should be used only for reference as mask tooling and wafer fabrication costs constantly change. The cost model proposed for calculating the production cost assumed by each project can serve as a basis for developing a fairer pricing model. The study of using MPW for low to medium-volume production is also very useful. It may help a customer deliver its product earlier to market using a low-cost fabrication program. The problem addressed in this paper becomes much simpler if the side-to-side wafer dicing constraint is removed.

Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper, we propose a methodology to explore reticle flooplan design space to minimize MPW production cost, facilitated by a new cost model and an efficient reticle floorplanning method. It is shown that a good floorplan saves 47% and 42% production cost with respect to a poor floorplan for small and medium volume production, respectively.

On-chip bus encoding was previously shown not viable for energy reduction based on same wire-pitch assumption. In this paper, we revisit this issue not only from the energy but also from the delay and codec overhead perspectives. With the same routing area for each encoding method, we show that all investigated methods including those using more redundant wires for crosstalk avoidance are not viable for an on-chip bus with a 0.18 /spl mu/m process technology from all perspectives. We also show that a wrong conclusion would be drawn if our methodology is not used. Such a study can be readily made for a more advanced process technology.

Multi-project wafer has become a low-cost avenue to gain access to more advanced process technology via amortizing mask cost among chips placed on the same reticle (called reticle floorplanning). Assuming chips have flexible dimensions, we propose a non-linear programming model for reticle floorplanning to optimize reticle area and make more chips with same width or height. The model allows co-existence of chips with fixed and flexible aspect ratios and can be solved within half an hour. For the test cases originally having few chips with same width or height, our floorplanning method achieves more than 50% reduction in wafers used. We also propose an effective dicing method that saves up to 40% of wafers.

Theorem 2 of the title paper (A.B. Kahng et al., ibid. vol. 18, pp.445-462, 1999) presents layout density bounds for any fixed r-dissection w-by-w window given the layout density of at least L and at most U for all w-by-w windows whose bottom left corners are at points (i(w/r), j(w/r)), i, j=0, 1, ..., r((n/w)-1) on an n-by-n layout plane. However, the bounds are not tight for certain combinations of U (L) and r. Here, the authors present an approach to obtaining the tight lower and upper bounds for all possible combinations of U (L) and r.

The closed-form formulas derived from the Markov chains depicting the bus-invert coding processes for even and odd bus widths are employed to compute switching activity and weight per bus transfer, to explain the diminishing returns with increasing bus width and to show the nonviability of partitioning a bus into smaller buses of odd number bits, etc. Probing into the codewords generated by the coding process, we obtain the same closed-form formulas as that obtained by the Markov-based approach. Our contributions form a superset over the previously published theoretical results and provide comprehensive background information for exploiting the bus-invert method for low-power applications.

This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates to the P and N channel transistors that drive the output pad. The slew rates are deliberately designed such that the N(P) transistor at the output stage will be turned off faster than the P(N) transistor is turned on for low-to-high (high-to-low) output transitions. It is demonstrated experimentally by HSPICE simulation that the off-chip driver designed by the proposed approach not only produces viable power-delay products, but also results in smaller noise.

The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment. Two releases of a 0.25 /spl mu/m standard cell library have been tested by these two benchmark circuits to ensure their quality.

A contemporary definition of VLSI placement problem is characterized by multiple objectives. These objectives are: timing, chip area, interconnection length and possibly others. In this paper, fuzzy logic has been used to facilitate multiobjective decision-making in placement for standard cell design style. A placement process has been defined in terms of linguistic variables, linguistic values and membership functions. Various objectives have been related by hierarchical fuzzy logic rules implemented as object-oriented programming objects. It is demonstrated that a designed fuzzy logic system is flexible in selecting goals and considering tradeoffs. Details of implementation, experimental results and comparisons with other systems are provided.>

An application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing is described. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs.>