In the simulation of large circuits, the CPU time for solving the resulting linear equations may exceed the time required for evaluating the circuit elements. The circuit size above which this occurs depends on the applied transistor model and is roughly 10/sup 4/ devices for a vectorizing table model. To further speed up large-scale circuit simulation, one therefore has to focus on the solution algorithm. In this paper the excessive propagation of fill-in elements during sparse matrix factorization is identified as the major source of the superlinear increase of solution time. The idea of truncating the fill-in propagation in a variable manner forms the basis for the construction of a hierarchical solver with the same robustness as Newton's method but much less effort for large circuits. The method was applied to MOS circuits with up to 63000 transistors and in all cases the predominance of the solution part was broken. The new algorithm can be used efficiently both on sequential and vector architectures.>

A simulation tool-box and its applications to computer-aided design and scaling of deep-submicron CMOS are presented. The simulation tools are grouped around a mixed level approach and cover a wide range of applications. Due to the mixed-level approach, fast table models and accurate numerical models can be combined simultaneously in a single circuit simulation. Device and circuit characteristics can be accurately represented as functions of technical parameters, even in the deep-submicron region. The application of the toolbox is demonstrated for some examples from the fields of device design and SRAM scaling. The gate-drain overlap and junction depth of 0.4- mu m devices are optimized with respect to circuit performance and device degradation. Different drain structures and supply voltages for 0.25- mu m devices are compared. Scaling of CMOS SRAM's from 0.7 to 0.4 mu m and finally to 0.25- mu m gate length is simulated. The relevance of device structure, design rules, and supply voltage for speed, power dissipation, and chip area are pointed out and their influence on circuit performance predicted.>

In most cases steady-state semiconductor device equations are solved simultaneously by Newton's method, by Gummel's decoupled nonlinear relaxation scheme, or a combination of both. A framework deriving such different iterative methods from underlying variable transformations is presented. Within that framework the introduction of a new variable establishes a new nonlinear relaxation scheme, which is significantly faster than Gummel's scheme in cases where it converges slowly, thereby avoiding the drawbacks of a simultaneous solution method. This relaxation scheme has been implemented in the two-dimensional device simulator GALENE II.>

Most numerical MOS-simulators are based on Gummel's nonlinear relaxation method, for which severe convergence problems arise above threshold. A new hierarchical approach for the numerical simulation of MOS-transistors (MOST's) is presented, which overcomes these shortcomings resulting in an improvement of convergence speed of more than one order of magnitude.

A modular circuit is defined as a combination of a certain number of k-modules, which are embedded in a carrier network. The modules may represent subcircuits of varying complexity down to single devices. Such modular circuits lend themselves to a description by a system of modular equations. MEDUSA is a user-oriented simulator which utilizes system modularity during the simulation process itself, i.e., for solving the underlying equations. This approach enables the consistent numerical solution of both the basic equations of several bipolar devices and the network equations for a circuit environment. Hence, MEDUSA in its present state is a merged device-circuit simulator meeting simultaneously the requirements of device and circuit design.