This paper presents a multi-language test planning system, which is based on a goal-tree based test methodology. Multi-language support is achieved by adding a common abstraction layer on the top of different language specific details. The effectiveness of this strategy is demonstrated by using this tool for testing VHDL and SystemC models of a GSM system.

This paper presents a high-level test planning system for validating DSP real number models. It uses a goal tree structure as a framework of test planning and documenting. The goal tree based test plans are linked to the test bench generator, which creates test benches for simulation. The simulation results are checked and fed back to the test plans and new test benches are created accordingly. A GUI-based integrated software system has been developed for test planning and test automation based on this methodology. To illustrate this methodology, this paper uses the Synthetic Aperture Radar system as a case study. Finally, completeness and effectiveness of the generated test set are evaluated using structural approaches. Results of test set compaction are also presented.

Parallel computer architectures and problem solving strategies for the consistent labeling problem are studied. Problem solving factors include: processor intercommunication methods, passing order, and selection of the initial processor to receive the problem.

Fault- tolerant characteristics of a Boolean n cube array of microprocessors are analyzed. Connectivity properties of the network graph are used to show that n processor or link failures are required to isolate a processor. For processor failures the network is shown to be n (one step) diagnosable. A testing algorithm is presented which can diagnose up to n processor failures.

A design procedure is presented for realizing multiple-valued sequential logic functions as tree structured networks of sequential universal logic modules (SULM's). Both definite and nondefinite finite state machines can be realized using this approach. The SULM employed is a multiple-valued multiplexer-flip-flop cascade that can be efficiently implemented in multiple-valued technologies.

Cellular spaces are shown to possess properties favorable to reconfiguration. As a first step in the direction of reconfigurable cellular spaces, this paper demonstrates the implementation of arbitrary finite-state machines in self-diagnosing cellular spaces. The results cover single cell failures caused by erroneous state transitions or by erroneous outputs. One of the attractive features of the implementation is the absence of any hard core components. As an intermediate step, it is shown how to transform any given cellular space into a self-diagnosing cellular space. The results demonstrate that the control structure (which is a finite-state machine) of any computing device can be implemented as a self-diagnosing entity without hard core.

Diagnosis of stuck-at faults (s-a-f's) in modular trees is studied. Detection conditions for each distinguishable s-a-f in a module are derived. For single s-a-f's, the detection conditions are easily partitioned to achieve fault location by performing a small number of additional tests. A multiple s-a-f that produces the same test result as a single s-a-f can be located by applying additional tests whose number grows with the tree depth. All other multiple s-a-f's are detected but cannot be located. In this paper location algorithms for combinational modular trees are presented in detail. They are then modified to locate faults in modular trees which realize arbitrary definite machines. Since a pair of these tree structures can be connected to realize arbitrary sequential machines, the results derived here are useful in diagnosing sequential machines. The ability to diagnose faults, combined with the fact that the function of the tree is easily altered, makes this structure attractive in reconfiguration applications. In particular, application to array processors is suggested.

Sufficient conditions are derived that make multidimensional bilateral arrays of combinational cells easily testable for single faults. These conditions are easily implemented during the initial design of the arrays. No restrictions are made on the interconnection patterns or directions of signal flow in the arrays. The conditions are equally applicable to synchronous and asynchronous arrays. No assumptions of stability are made. Any functional fault in a single cell will be detected as long as the failed cell is still combinational. The test sequence is preset and grows linearly with the size of the array.

An alternative design procedure is presented for the implementation of finite-state Moore machines as universal modular trees (UMT's). A machine property is shown to provide a design goal in the tree depth. Design specification is made heuristically by labeling transitions on a shift register state diagram. Programming of feedback and output trees is accomplished with a template tree. The procedure is felt to be more prone to reaching minimal tree depth and more expository of design choices (an aid in fault reconfiguration) than previous design procedures.

When a specific type of network is required, the function to be realized limits the amount of fault tolerance that can be achieved. Parameters of functions that affect the maximum obtainable fault tolerance and the maximum obtainable diagnosability are investigated for several types of combinational memoryless) networks.

The problem of detecting faults in arbitrarily large unilateral iterative arrays of combinational cells when any number of modules can be faulty and each module can fail in an arbitrary manner has been considered. A simple design criterion has been given which if incorporated makes the array easily diagnosable. Methods of deriving test sets for the modified arrays, which requires rather trivial computations and no complicated algorithms, have been given. The tests obtained are largely independent of the behavior of the individual modules in the array and are efficient. It has also been shown that Maitra cascades, group cascades, and cutpoint cellular arrays are testable without any modification. Methods of obtaining test sets for these special arrays have been given. Arrays of more than two dimensions have also been considered.

A class of universal finite-state machine structures employing arrays of identical modules is shown to be capable of dynamic repair by the process of reconfiguration. Coverage on the order of 98 percent of all stuck-at faults is demonstrated with no redesign of the array being necessary. After specifying a formal model for the array structure, a complete theory is developed capable of determining the minimal number of configurations necessary to obtain maximal coverage of stuck-at faults without redesigning the network. Inherent redundancy in the array structure results in this unusual capability. Many faults are also tolerated in each system configuration.

A formal model for the study of reliable combinational networks is introduced and used to determine network properties conducive to the location of faults. The usual concept of fault location is generalized to be an interval on the partially ordered set of subsets of network nodes that classifies nodes into three disjoint sets: a faulty set, a fault-free set, and an indeterminate set. After developing basic properties of locatable faults, necessary and sufficient conditions for a fault to be locatable in an arbitrary network are stated and proven.