A grid refinement methodology suitable for arbitrary spatial dimensions and geometries is developed. Using just the structural description of a device-specified by the user or taken directly from the output of a process simulator-strategies for creating an initial grid are proposed, embodying whatever knowledge the simulator can have about how the solution will behave. After solving the PDEs, a grid is adapted by examining the local error involved in the discretization process. A set of procedures is proposed for this purpose and shown to be nearly optimal in terms of cost and efficiency. The key to implementing a robust and efficient scheme lies in the choice of a suitable error indicator; it is shown that some of the more obvious candidates can perform quite poorly. The initial grid construction and error indicator schemes are used to show how the full adaptation procedure works on some practical examples.>

A hybrid finite-element method to discretize the continuity equation in semiconductor device simulation is given. Within each element of a finite element discretization, the current is uniquely determined by nodal values of the density and the potential. The authors use the integrability condition for a system of partial differential equations to obtain the equations that determine the current within the element. They then satisfy the continuity in the current flow across interelement boundaries in a weak sense. They have found that the method works in any dimension and for (d-dimensional) simplexes as well as for quadrilaterals, bricks, prisms, and so on, although they have no proof that it will not break down in particular cases.>

An efficient self-consistent device simulator coupling Poisson equation and Monte Carlo transport suitable for general silicon devices, including those with regions of high doping/carrier densities, is discussed. Key features include an original iteration scheme and an almost complete vectorization of the program. The simulator has been used to characterize nonequilibrium effects in deep submicron nMOSFETs. Substantial overshoot effects are noticeable at gate lengths of 0.25 mu m at room temperatures.>

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V. Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained.>

In this paper, we present an overview of the physical principles and numerical methods used to solve the coupled system of nonlinear partial differential equations that model the transient behavior of silicon VLSI device structures. We also describe how the same techniques are applicable to circuit simulation. A composite linear multistep formula is introduced as the time-integration scheme. Newton-iterative methods are exploited to solve the nonlinear equations that arise at each time step. We also present a simple data structure for nonsymmetric matrices with symmetric nonzero structures that facilitates iterative or direct methods with substantial efficiency gains over other storage schemes. Several computational examples, including a CMOS latchup problem, are presented and discussed.