Proposes a method for compressing programs in embedded processors where the instruction memory size dominates the cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM and i386 instruction sets and achieve an average size reduction of 39%, 34% and 26%, respectively, for SPEC CINT95 programs.

Decoupled architectures provide a key to the problem of sustained supercomputer performance through their ability to hide large memory latencies. When a program executes in a decoupled mode the perceived memory latency at the processor is zero; effectively the entire physical memory has an access time equivalent to the processor's register file, and latency is completely hidden. However, the asynchronous functional units within a decoupled architecture must occasionally synchronize, incurring a high penalty. The goal of compiling and optimizing for decoupled architectures is to partition the program between the asynchronous functional units in such a way that latencies are hidden but synchronization events are executed infrequently. This paper describes a model for decoupled compilation, and explains the effectiveness of compilation for decoupled systems. A number of new compiler optimizations are introduced and evaluated quantitatively using the Perfect Club scientific benchmarks. We show that with a suitable repertoire of optimizations, it is possible to hide large latencies most of the time for most of the programs in the Perfect Club.

This paper examines the effectiveness of decoupling as an optimization technique for high-performance computer architectures. Decoupled access execute architectures are described, and the concept of control decoupling is introduced and justified. A description of a highly-decoupled architecture is given, and a metric for the effectiveness of decoupling on particular programs, the Loss of Decoupling frequency is introduced. Finally, a number of real benchmark programs are examined and the applicability of decoupling them is analyzed.

Article Free Access Share on A semantics-directed partitioning of a processor architecture Authors: Peter L. Bird Advanced Computer Research Institute, 1, Blvd Vivier-Merle, 69443 Lyon, Cedex 03 France Advanced Computer Research Institute, 1, Blvd Vivier-Merle, 69443 Lyon, Cedex 03 FranceView Profile , Uwe F. Pleban Applied Dynamics International, 3800 Stone School Rd., Ann Arbor, MI Applied Dynamics International, 3800 Stone School Rd., Ann Arbor, MIView Profile Authors Info & Claims Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on SupercomputingAugust 1991 Pages 702–709https://doi.org/10.1145/125826.126162Published:01 August 1991Publication History 1citation152DownloadsMetricsTotal Citations1Total Downloads152Last 12 Months5Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We introduce a storage system control structure which employs lookahead to minimize the incidence of bank collisions for operand references in memory systems with interleaved banks.We show that by employing lookahead a memory system achieves high data throughput with only a small interleave factor.5'imulation results show that an 8 bank system with lookahead performs as well, or better, than a 32 bank system without Iookahead.A Iookahead controller simplifies the design of bank management hardware, thus reducing the complexity of high throughput memory designs.