EDBT 2026 Demo / reviewers in the wild / expert
Diego Melpignano
dblp:27/3091
· DBLP profile ↗
8ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0005-0810-0828ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 4 · 1 since 2021Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Edge and fog computing · 77% Internet of things and sensor networks · 23% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 50% Hardware accelerators and domain-specific architectures · 38% GPUs and heterogeneous computing · 12% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 5 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Efficient and distributed learning › edge computing › on-device machine learning
TinyML |
0.3 | 1 | 2025 | Poster Abstract: ST AIoT Craft - A No-Code / Low-Code Cloud Solution for Edge AI Management in Smart Sensors · SenSys 2025 |
Hardware accelerators and domain-specific architectures
many-core accelerator |
0.1 | 1 | 2012 | Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications · DAC 2012 |
Parallel and multicore computing › many-core systems
many-core computing |
0.1 | 1 | 2012 | Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications · DAC 2012 |
GPUs and heterogeneous computing › heterogeneous programming models
OpenCL |
0.0 | 1 | 2012 | Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications · DAC 2012 |
Parallel and multicore computing
parallel programming models |
0.0 | 1 | 2012 | Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications · DAC 2012 |
Methods — techniques the papers use, named apart from their topics
OpenCV · 0.1OpenCL · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Poster Abstract: ST AIoT Craft - A No-Code / Low-Code Cloud Solution for Edge AI Management in Smart SensorsabstractCurrent sensor-gateway-cloud solutions for machine learning (ML) life cycle development require extensive coding, hardware, and software expertise. We present ST AIoT Craft, the first no-code/low-code online platform for training, deploying, and managing distributed artificial intelligence of things (AIoT) and big data. The framework provides user-interface dashboards and web applications for sensor data logging and management, dataset preprocessing and visualization, automatic tinyML for in-sensor processors and microcontrollers, and end-to-end Internet of things (IoT) system setup and monitoring. The tools allow developers to manage intelligent IoT devices, gateways, and cloud infrastructure directly from a web browser. ST AIoT Craft is accessible at https://staiotcraft.st.com/. Mahesh Chowdhary, Swapnil Sayan Saha, Mridupawan Das, Jana Scukova, Miroslav Batek, Lisa Trollo, Davide Sergi, Davide Aliprandi, Alberto Villa, Andrea Palmieri, Mohammed Maher Jouini, Daniele Alfonso, Diego Melpignano |
SenSys | 13 |
| 2013 | Improving simulation speed and accuracy for many-core embedded platforms with ensemble modelsabstractIn this paper, we introduce a novel modeling technique to reduce the time associated with cycle-accurate simulation of parallel applications deployed on many-core embedded platforms. We introduce an ensemble model based on artificial neural networks that exploits (in the training phase) multiple levels of simulation abstraction, from cycle-accurate to cycle-approximate, to predict the cycle-accurate results for unknown application configurations. We show that high-level modeling can be used to significantly reduce the number of low-level model evaluations provided that a suitable artificial neural network is used to aggregate the results. We propose a methodology for the design and optimization of such an ensemble model and we assess the proposed approach for an industrial simulation framework based on STMicroelectronics STHORM (P2012) many-core computing fabric. Edoardo Paone, Nazanin Vahabi, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley |
DATE | 5 |
| 2012 | Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applicationsabstractP2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm2 with 2W power consumption (worst-case). P2012 can run standard OpenCL™ and proprietary Native Programming Model SW components to achieve the highest level of control on application-to-resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs. Diego Melpignano, Luca Benini, Eric Flamand, Bruno Jego, Thierry Lepley, Germain Haugou, Fabien Clermidy, Denis Dutoit |
DAC | 1 |
| 2012 | P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing acceleratorabstractP2012 is an area- and power-efficient many-core computing fabric based on multiple globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine-grained power, reliability and variability management. Clusters feature up to 16 processors and one control processor with independent instruction streams sharing a multi-banked L1 data memory, a multi-channel DMA engine, and specialized hardware for synchronization and scheduling. P2012 achieves extreme area and energy efficiency by supporting domain-specific acceleration at the processor and cluster level through the addition of dedicated HW IPs. P2012 can run standard OpenCL and OpenMP parallel codes well as proprietary Native Programming Model (NPM) SW components that provide the highest level of control on application-to-resource mapping. In Q3 2011 the P2012 SW Development Kit (SDK) has been made available to a community of R&D users; it includes full OpenCL and NPM development environments. The first P2012 SoC prototype in 28nm CMOS will sample in Q4 2012, featuring four clusters and delivering 80GOPS (with single precision floating point support) in 15.2mm2with 2W power consumption. Luca Benini, Eric Flamand, Didier Fuin, Diego Melpignano |
DATE | 4 |
| 2008 | APOS: Adaptive Parameters Optimization Scheme for Voice over IEEE 802.11gabstractIn this paper we present APOS, a method for dynamically adapting the parameters of IEEE 802.11 g to the estimated system state, with the aim of enhancing the quality of a voice communication between a mobile station and a remote peer node. The system state is estimated based on a number of counters that are collected by the MAC layer of the mobile station, regarding the number of successful and unsuccessful transmission/reception events, channel busy periods and idle slots. These statistics are processed to estimate the collision probability and the signal to noise ratio at the receiver side. Hence, a mathematical model is used to get the expected end-to-end network performance in terms of throughput, delay and packet error rate, for different settings of some PHY and MAC parameters, such as the modulation/coding scheme and the retransmission limit. The setting that is estimated to maximize the quality of service for the end user is then selected. Unlike other optimization mechanisms proposed in literature, APOS is totally stand-alone and standard compliant. In fact, APOS makes use of local information that can be collected from the Network Interface Card, and no explicit interactions with the other devices in the network is required. Nicola Baldo, Federico Maguolo, Simone Merlin, Andrea Zanella, Michele Zorzi, Diego Melpignano, David Siorpaes |
ICC | 6 |
| 2008 | GORA: Goodput Optimal Rate Adaptation for 802.11 Using Medium Status EstimationabstractRate adaptation for 802.11 has been deeply investigated in the past, but the problem of achieving optimal rate adaptation with respect not only to channel-related errors but also to contention-related issues (i.e., collisions and variations in medium access times) is still unsolved. In this paper we address this issue by proposing (1) a practical definition of the medium status in a multi-user 802.11 scenario in terms of channel errors, MAC collisions and packet service times, and a method for its estimation based on measurements; (2) an analytical model of the goodput performance as a function of the Medium Status; (3) a rate adaptation algorithm, called goodput optimal rate adaptation (GORA), which is based on this model. Unlike other rate adaptation schemes proposed in literature, which require either modifications to the IEEE 802.11 standard or cooperation among nodes, GORA is totally stand-alone and standard compliant. In fact, the Medium Status Estimation used by GORA is obtained by using standard MAC counters that are commonly collected by commercial MAC drivers, and no explicit interactions with the other devices in the network is required. Therefore, GORA offers the advantage of being readily deployable on real devices. The performance of GORA is evaluated through NS2 simulations which reveal that, as expected, GORA outperforms other well- known rate adaptation algorithms in several scenarios and can be used as a new reference benchmark. Nicola Baldo, Federico Maguolo, Simone Merlin, Andrea Zanella, Michele Zorzi, Diego Melpignano, David Siorpaes |
ICC | 6 |
| 2008 | Unified Link Layer API: A generic and open API to manage wireless media access
Mahesh Sooriyabandara, Tim Farnham, Costas Efthymiou, Matthias Wellens, Janne Riihijärvi, Petri Mähönen, Alain Gefflaut, José Antonio Galache, Diego Melpignano, Arthur van Rooijen |
Comput. Commun. | 9 |
| 2002 | Wireless IP adaptation layer: an open performance enhancement protocol architectureabstractHeterogeneous networks require mechanisms for transparent protocol boosting in legacy systems and adaptive support for seamless interoperability between different wireless access methods. In this paper, we present an open performance enhancement protocol architecture that is developed to provide a generic protocol enhancing proxy (PEP) service for wireless access points and terminals. First, we describe the basic architecture and philosophy of our approach. Then some illustrative protocol boosting modules are presented with results. Finally, we describe the future work that is required in order to make the so-called wireless adaptation layer (WAL) useful in production quality environments. Petri Mähönen, Luis Muñoz, Diego Melpignano, George Orphanos, Zach Shelby, Timo Saarinen, Marcelo H. García |
PIMRC | 3 |