Voltage overscaling, or undervolting, is an enticing approximate technique in the context of energy-efficient Deep Neural Network (DNN) acceleration, given the quadratic relationship between power and voltage. Nevertheless, its very high error rate has thwarted its general adoption. Moreover, recent undervolting accelerators rely on 8-bit arithmetic and cannot compete with state-of-the-art low-precision (<8b) architectures. To overcome these issues, we propose a new technique called Guarded Aggressive underVolting (GAV), which combines the ideas of undervolting and bit-serial computation to create a flexible approximation method based on aggressively lowering the supply voltage on a select number of least significant bit combinations. Based on this idea, we implement GAVINA (GAV mIxed-Precision Accelerator), a novel architecture that supports arbitrary mixed precision and flexible undervolting, with an energy efficiency of up to 89 TOP/sW in its most aggressive configuration. By developing an error model of GAVINA, we show that GAV can achieve an energy efficiency boost of 20% via undervolting, with negligible accuracy degradation on ResNet-18.

Efficiently computing Deep Neural Networks (DNNs) has become a primary challenge in today's computers, especially on devices targeting mobile or edge applications. Recent progress on Post-Training Quantization (PTQ) and Quantization-Aware Training (QAT) has shown that the key to high energy efficiency lies in executing deep learning models with low- (8- to 5-bit) or ultra-low-precision (4- to 2-bit). Unfortunately, current Central Processing Unit (CPU) architectures and Instruction Set Architectures (ISAs) present severe limitations on the range of data sizes supported to compute DNN kernels. In this work, we presentMix-GEMM, a hardware-software co-designed architecture that enables RISC-V processors to efficiently compute arbitrary mixed-precision DNN kernels, supporting all data size combinations from 8- to 2-bit. By applyingbinary segmentation, our architecture can scale its throughput by decreasing the data size of the operands, resulting in a flexible approach capable of leveraging state-of-the-art QAT and PTQ to achieve high energy efficiency at a very low cost. Evaluating ourMix-GEMMarchitecture in a dual-issue in-order RISC-V processor shows that we are able to boost its performance and energy efficiency by up to$44\times$and$11\times$with respect to the baseline processor, with an area overhead of only 2%. This allows our extended processor to execute state-of-the-art DNNs with significantly higher performance and energy efficiency than the standard FP32 precision, while retaining almost the same model accuracy.

Systolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications (GeMMs), but computing convolutions with this primitive involves transforming the 3-D input tensor into an equivalent matrix, which can lead to an inflation of the input data, increasing the OFF-chip memory traffic which is critical for energy efficiency. In this work, we propose a GeMM-based systolic array accelerator that uses a novel data feeder architecture to perform ON-chip, on-the-fly convolution lowering (also known as im2col), supporting arbitrary tensor and kernel sizes as well as strided and dilated (or atrous) convolutions. By using our data feeder, we reduce memory transactions and required bandwidth on state-of-the-art CNNs by a factor of two, while only adding an area and power overhead of 4% and 7%, respectively. Application specific integrated circuit (ASIC) implementation of our accelerator in 22-nm technology fits in less than 1.1 mm 2 and reaches an energy efficiency of 1.10 TFLOP/sW with 16-bit floating-point arithmetic.

We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.

We present a set of sensors that enable a built-in test in RF circuits. The key characteristic of these sensors is that they are non-intrusive, that is, they are not electrically connected to the RF circuit, and, thereby, they do not degrade its performances. In particular, the presence of spot defects is detected by a temperature sensor, whereas the performances of the RF circuit in the presence of process variations are implicitly predicted by process sensors, namely dummy circuits and process control monitors. We discuss the principle of operation of these sensors, their design, as well as the test strategy that we have implemented. The idea is demonstrated on an RF low noise amplifier using post-layout simulations.

In the present paper we analyze that DC temperature measurements of the silicon surface can be used to monitor the high frequency status and performances of class A RF Power Amplifiers. As a proof of concept, we present experimental results obtained with a 65 nm CMOS IC that contains a 2 GHz linear class A Power Amplifier and a very simple differential temperature sensor. Results show that the PA output power can be tracked from DC temperature measurements.

In this paper we demonstrate that the steady state temperature increase due to the power dissipated by the circuit under test can be used as observable to test the gain of a 2GHz linear class A Power Amplifier. As a proof of concept, we use two strategies to monitor the temperature: a temperature sensor embedded within the same silicon die, which can be used for a BIST approach, and an Infra Red camera, with applications to failure analysis and product debugging.

In this presentation we cover how to use low frequency or DC temperature measurements to observe figures of merit of high frequency analogue circuits.

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.

The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements on the silicon surface. In this paper, the frequency response of a RF LNA is observed by measuring spectral components of the sensed temperature. Results prove that temperature can be used to debug and observe figures of merit of analog blocks in a RFIC. Experimental measurements have been done in a 0.25 mum CMOS process. Laser probing techniques have been used as temperature sensors; specifically, a thermoreflectometer and a Michaelson interferometer.

In this work a new technique for the observation and characterization of high-frequency electrical characteristics of analog and radio frequency integrated circuits (RFIC) by on-chip frequency-domain thermal measurements is proposed. The analysis presented confirms that low-frequency spectral components of the temperature sensed close to analog circuits contain information about some high-frequency characteristics of the circuits observed. The feasibility of this RF testing technique is confirmed experimentally. It is non-invasive and can be implemented with a very small area overhead. The technique is applied, as an example, to obtain some electrical characteristic of an RF low noise amplifier (LNA)

Measuring techniques of the die surface temperature in integrated circuits are reported as very appropriate for failure analysis, for thermal characterization, and for testing modern devices. The paper is arranged as a survey of techniques oriented towards measuring the temperature dynamics of the circuit surface and presenting and discussing both the merits and drawbacks of each technique with regard to the accuracy, reliability and efficiency of the measurements. Two methods are presented in detail: laser probing methods, based on interferometry and thermoreflectance, and embedded CMOS circuit sensors. For these techniques, the physical principles, the state of the art in figures of merit and some application examples are presented

Temperature is a physical magnitude that can be used as an observable quantity for IC testing purposes. The authors discuss in this paper the suitability of two temperature measuring strategies applicable to standard CMOS integrated circuits: a laser interferometer and a differential fully CMOS built-in temperature sensor.

By measuring the temperature at some points of an IC during a test procedure, defects can be detected (fault testing). With a simple processing of the measured temperature waveform, the distance between the temperature monitoring point and the activated defect can be derived. This paper presents four temperature measuring strategies to determine this distance for diagnosis purposes.

Temperature can be used as a test observable: some failures when activated produce an increase in local power dissipation, changing the surface thermal map of the IC, being detectable with built-in thermal sensors. In this work, both the feasibility of this testing technique and the generation of the specific test pattern are discussed.

A new testing alternative based on thermal wave propagation is proposed. Some failures, when activated, produce an increase in local power dissipation at various points. A thermal wave is generated by this increase and can be used as a test observable. In this paper, both the thermal wave and the heat sources that appear for a set of faults are characterised and a built-in sensing strategy based on differential considerations is analysed.