ABSTRACT The functional capabilities of radio‐frequency identification (RFID) tags are rapidly increasing. Therefore, they can no longer be treated as pure bar‐code substitute, but they should be considered as computing devices. Modern tags are able to store and compute data, or even hold sensors. To draw full advantage from the increased functionality of the tags, it will become important to integrate these tags into the Internet of Things (IoT), that is, enable two‐way end‐to‐end communication over the Internet. Powerful application scenarios can be developed when communication with tags can be established via the network. We introduce the concept of Mobile‐IPv6‐enabled RFID tags to enable a two‐way communication via IPv6. Mobile IPv6 allows integration of passive low‐cost RFID tags into the IoT in a transparent and compatible way. Like the “traditional” Internet, many applications can only be built upon secure communication. Therefore, it is essential to provide securing mechanisms. For the Internet, Internet Protocol Security (IPsec) is used to secure the connection between two nodes. In this paper, we want to define security services analog to IPsec for communication with RFID tags. We analyze the cryptographic capabilities of current RFID tags and build a security layer to enable a secure end‐to‐end connection between tags and other nodes in the net. Copyright © 2011 John Wiley & Sons, Ltd.

This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semicustom design flows. Contrary to other publications, a complete architecture (even including CBC mode) that is scalable in terms of throughput and in terms of the used key size is described. Similarities of encryption and decryption are utilized to provide a high level of performance using only a relatively small area (10,799 gate equivalents for the standard configuration). This performance is reached by balancing the combinational paths of the design. No other published AES hardware architecture provides similar balancing or a comparable regularity. Implementations of the fastest configuration of the architecture provide a throughput of 241 Mbits/sec on a 0.6 /spl mu/m CMOS process using standard cells.