EDBT 2026 Demo / reviewers in the wild / expert
David K. Probst
dblp:27/375
· DBLP profile ↗
6ranked-venue papers
4as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 4 · 3 first-authorSystems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Automata and formal languages · 44% Automated reasoning and model checking · 44% Algorithms and data structures · 6% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 57% Processor architecture and microarchitecture · 33% Interconnection networks and networks-on-chip · 10% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
VLSI design |
0.0 | 2 | 1990 | Optimal VLSI Dictionary Machines Without Compress Instructions · IEEE Trans. Computers 1990 Abstract Specification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network Implementations · IEEE Trans. Computers 1988 |
Automated reasoning and model checking
real-time verification |
0.0 | 1 | 1993 | Verifying Timed Behavior Automata with Input/Output Critical Races · CAV 1993 |
Automata and formal languages
timed automata |
0.0 | 1 | 1993 | Verifying Timed Behavior Automata with Input/Output Critical Races · CAV 1993 |
Processor architecture and microarchitecture › parallel computer organization
dictionary machine |
0.0 | 1 | 1990 | Optimal VLSI Dictionary Machines Without Compress Instructions · IEEE Trans. Computers 1990 |
Interconnection networks and networks-on-chip › network topology
linear network |
0.0 | 1 | 1990 | Optimal VLSI Dictionary Machines Without Compress Instructions · IEEE Trans. Computers 1990 |
Computational complexity
algebraic complexity |
0.0 | 1 | 1979 | A Family of Algorithms for Powering Sparse Polynomials · SIAM J. Comput. 1979 |
Algorithms and data structures
symbolic computation |
0.0 | 1 | 1979 | A Family of Algorithms for Powering Sparse Polynomials · SIAM J. Comput. 1979 |
Methods — techniques the papers use, named apart from their topics
separation of concerns · 0.0VLSI design · 0.0synchronous data types · 0.0parnas trace method · 0.0abstract specification · 0.0sequential algorithms · 0.0binomial expansion · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Verifying Timed Behavior Automata with Input/Output Critical Races
David K. Probst, Hon Fung Li |
CAV | 1 |
| 1990 | Optimal VLSI Dictionary Machines Without Compress InstructionsabstractSeveral designs are presented for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The initial design objectives included: (1) single-cycle operability of host-issued modify and query commands (no compress instructions), (2) complete processor utilization (no waste processors), and (3) optimal 2 log n response times, where n is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously. They were forced to abandon objective (3), instead achieving a slightly weaker objective, namely, near-optimal (2 log n+R) response times, where R is the time for a round trip through the particular prenetwork used to connect the host to the roots of the query trees in the logarithmic network. Both sorted and unsorted versions of dictionary machines are presented. Those with orthogonal command networks achieve all objectives; those without orthogonal networks achieve only the first and third.> Hon Fung Li, David K. Probst |
IEEE Trans. Computers | 2 |
| 1988 | Abstract Specification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network ImplementationsabstractA combined methodology is presented for specifying abstract synchronous data types and proving the correctness of systolic network implementations. It is shown that an extension of the Parnas trace method of specifying software modules containing distinct access programs yields a natural method of specifying abstract synchronous data types that possess distinct access operators and are intended for implementation in VLSI. Associated systematic proof techniques are presented, and the correctness of several novel systolic network implementations of familiar data types is established. The methodology appears to be naturally suited to systolic network implementations with their associated rippling of control flow and data flow. The important distinction between systolic control-flow networks and systolic data-flow networks is presented.> David K. Probst, Hon Fung Li |
IEEE Trans. Computers | 1 |
| 1987 | A fast, low-space algorithm for multiplying dense multivariate polynomialsabstractThis paper presents an improved adaptive hybrid algorithm for multiplying dense multivariate polynomials that is both time and space efficient. The hybrid algorithm makes use of two families of univariate algorithms, one Karatsuba based and the other DFT based, which are applied recursively to solve the multivariate problem. The hybrid algorithm is adaptive in that particular univariate algorithms are selected at run time to minimize the time complexity; an order-of-magnitude speedup with respect to classical multiplication is achieved over the entire practical range except for very small problems. Empirical investigation shows that most of the theoretical superiority is maintained in actual implementation. The largest contribution to the space requirements of the total algorithm is determined by the univariate algorithm used for the outermost variable; except for quite small problems, selecting univariate algorithms to minimize run time almost always leads to situations where the space requirements of the total algorithm are extremely close to the space required merely to store the result. Vangalur S. Alagar, David K. Probst |
ACM Trans. Math. Softw. | 2 |
| 1980 | Corrigendum: A Family of Algorithms for Powering Sparse PolynomialsabstractPrevious article Full AccessCorrigendum: A Family of Algorithms for Powering Sparse PolynomialsDavid K. Probst and Vangalur S. AlagarDavid K. Probst and Vangalur S. Alagarhttps://doi.org/10.1137/0209033PDFBibTexSections ToolsAdd to favoritesExport CitationTrack CitationsEmail SectionsAbout"Corrigendum: A Family of Algorithms for Powering Sparse Polynomials." SIAM Journal on Computing, 9(2), p. 439 Previous article FiguresRelatedReferencesCited byDetails Volume 9, Issue 2| 1980SIAM Journal on Computing History Published online:13 July 2006 InformationCopyright © 1980 Society for Industrial and Applied MathematicsPDF Download Article & Publication DataArticle DOI:10.1137/0209033Article page range:pp. 439-439ISSN (print):0097-5397ISSN (online):1095-7111Publisher:Society for Industrial and Applied Mathematics David K. Probst, Vangalur S. Alagar |
SIAM J. Comput. | 1 |
| 1979 | A Family of Algorithms for Powering Sparse PolynomialsabstractWe discuss four new algorithms from a family of algorithms for computing integer powers of sparse polynomials. The four algorithms form a sequence of successively better algorithms; even the first member of the sequence shows an improvement in the leading term of the cost function in comparison with the best previously known binomial-expansion algorithm. To quote one result, if f is a 32-term sparse polynomial, computing $f * f^9 $ takes $8.75 \times 10^9 $ multiplications, while the best new algorithm computes $f^{10} $ from scratch using $1.125 \times 10^9 $ multiplications. The time and space analyses given support the conjecture that the best new algorithm is optimal for time and space within the family of sequential binomial-expansion algorithms for this problem. If the input polynomial has t terms, then the nth power may be computed by this algorithm with a time complexity of \[ \frac{{t^n }}{{n!}} + t^{n - 1} \left[ \frac{1}{{2(n - 2)!}} + \frac{1}{{2^{n - 2} (n - 1)!}}\right] + O(t^{n - 2} ),\quad n > 2 , \] and a space complexity of \[ \frac{{t^{n - 1} }}{{2^{2n - 4} (n - 1)!}} + O(t^{n - 2} ),\quad n > 2. \] David K. Probst, Vangalur S. Alagar |
SIAM J. Comput. | 1 |