Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32/spl times/32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 /spl mu/m CMOS technology and tested to operate correctly at 240 MHz.

Proposes and analyzes a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS). A multicast knockout principle, an extension of the generalized knockout principle, is applied in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude. In the proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributively so that a large switch size is achievable. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric (i.e., the multicast grouping network) with a single type of chip. A two-stage structure of the multicast output buffered ATM switch (MOBAS) is described. The performance of the switch fabric in cell loss probability is analyzed, and the numerical results are shown. The authors show that a switch designed to meet the performance requirement for unicast calls will also satisfy multicast calls' performance. A 16/spl times/16 ATM crosspoint switch chip based on the proposed architecture has been implemented using CMOS 2-/spl mu/m technology and tested to operate correctly.>

In the paper, the fault detection, fault location, and reconfiguration schemes for a large-scale multicast output buffered ATM switch (MOBAS) are proposed. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric with a single type of chip. It is difficult to achieve fault tolerance in binary self-routing networks without adding additional switching planes, stages, or switching elements in order to have multiple paths due to their characteristics of a unique routing path between any input and output pair. However, since the MOBAS intrinsically has multiple paths between any input and output, it is inherently robust for faults without need to add any additional switching elements. The fault-tolerance of the MOBAS is shown through the performance analysis of the MOBAS under various fault conditions.>

Chao and Choe (1993) proposed a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS). Four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributedly in the MOBAS, which allows the switch to grow. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric with a single type of chip. Multicast knockout principle, an extension of generalized knockout principle, is applied to construct the entire switch fabric so as to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude. In the present paper, the authors analyze a two-stage MOBAS in its cell loss rate and present some numerical results. They show that a switch that is designed, based on the multicast knockout principle, to meet the performance requirement for unicast calls will also satisfy the performance requirement for multicast calls.>