This design contest document proposes a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. A FVF filter, current mirror, and common-source amplifier are employed to configure the FBPEC. The FBPEC employs the characteristics of the FVF filter to reduce the current consumption and increase the gain at specific frequencies. A 0.18 μm CMOS process is used to design and fabricate the proposed LDO. Compared to the general configuration LDO by measurement results, the proposed LDO exhibits an enhanced power supply rejection ratio (PSRR) up to 18 dB at frequencies exceeding 8 kHz. Moreover, the quiescent current of the proposed LDO at no-load is 648 nA. The proposed LDO exhibits a good figure-of-merit score compared to those of previous works, suggesting that the proposed circuit is an effective solution for use in wearable low-power EEG recording devices.

In this design contest document, measurement results demonstrate the effectiveness of a designed low current consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. When reconstructing with a frequency bases, the reduction of biased 1/f noise is more important than frequency-unbiased white noise. Therefore, we designed an amplifier that reduces 1/f noise rather than white noise, while reducing power consumption, and employed it in the system. The designed amplifier is based a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which used for low-noise amplifier (LNA). According to measurements of the designed CCIA, the power consumption is 0.36 μW/channel, it has the lower power consumption compared to amplifiers designed for similar applications in the past. The input referred noise (IRN) excluding the hum of the power supply was 3.3 μVrms. The measured IRN and simulations were used to confirm the effect of noise from CCIA on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions is 0.008. This result shows that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by making use of the sparsity of EEG in the frequency domain.

Achieving power savings while maintaining accuracy is essential for wireless electroencephalogram (EEG) measurement devices, enabling them to be lighter with smaller batteries and longer operating times. To meet this requirement, we developed a wireless EEG transmission system that utilizes compressed sensing (CS) with random undersampling to achieve high-accuracy reconstruction while reducing sensing and transmission power. As a key feature of the implemented system, we designed and employed a suitable basis from previously obtained EEG signals for the block sparse Bayesian learning algorithm. Measurements showed that our system achieved significant power savings with a compression ratio of 6, consuming only 72 µW, which is lower than that reported in the latest CS-based study. Notably, despite the reduced power consumption, we reduced the normalized mean square error to 0.116, achieving more than twice the reconstruction accuracy reported in the previous study.

This study presents a solution to achieve low power consumption by the intermittent operation of low-noise amplifiers (LNAs) for wireless electroencephalographs, that need a smaller battery. The LNA operates intermittently synchronized with the sampling timing of the analog-to-digital converter (ADC) by using the random undersampling matrix utilized in a previously proposed compressed sensing (CS) electroencephalogram measurement system. Designed using a 0.18 μm CMOS process, the LNA includes an intermittent operation circuit. The simulation results, the start-up time of the LNA was set to 4ms and the intermittent operation was performed at compression ratio of 4.17 based on a sampling frequency of 200Hz. The intermittent operation reduced power consumption by 58% compared to constant operation. The normalized mean square error (NMSE) was used to evaluate the influence of intermittent LNA operation on the reconstruction accuracy of CS. The difference in NMSE between intermittent and constant operation was only 9% on average over 25 frames. This indicates that intermittent operation minimally influenced the reconstruction accuracy.

This paper presents an extremely low-voltage flip-flop (ELVFF) consisting of recursive stacking body-bias logic gates with the capability of operating at extremely low supply voltages. The ELVFF is based on a conventional NAND latch based flip-flop (NLFF), and consists of three-times-recursive-stacking body-bias NANDs (3RSBB-NANDs) and onetime-recursive-stacking body-bias inverters (1RSBB-INVs). The recursive-stacking and body-bias techniques provide an effective strategy for achieving ELV operation. The combination of these techniques allows for the enhancement of both the voltage gain and voltage swing of logic gates, thereby enabling the ELVFF to operate at extremely low supply voltages. Simulation results in a standard 180-nm CMOS process with a deep-n-well option indicated that our proposed ELVFF was capable of operating at an extremely low supply voltage of 40 mV. Measurement results also demonstrated that the ELVFF stored and maintained the correct logic with an amplitude of 27 mV and a power dissipation of 6.03 nW at a 39-mV power supply. The ELVFF is suitable for sub-100-mV ELV applications, such as energy harvesting, at the cost of an increased number of transistors, area, power, and delay time.

The application of compressed sensing has gained interest for its potential to achieve low power consumption in wireless electroencephalogram (EEG) measurement devices. In this study, we propose a system that utilizes the EEG basis (EEGB) matrix, allowing for the same reconstruction accuracy as a discrete cosine transform (DCT) matrix, which is a well known conventional matrix, while realizing low-power consumption in a low noise amplifier (LNA). Our theoretical analysis reveals that, for a 5x compression aiming at an equivalent normalized mean square error of 0.25, the use of the EEGB matrix can decrease the power consumption of the LNA by approximately 75% compared to using a DCT matrix.

This paper presents a programmable differential bandgap reference (DBGR) for ultra-low-power IoT (Internet-of-Things) edge node devices. The circuit consists of a bandgap reference (BGR) based current generator (CG) and differential voltage generator (DVG). The BGR-based CG generates a current and a voltage, and the DVG generates another voltage from the current. A differential voltage reference can be obtained by taking the voltage difference from the voltages. The circuit can produce a programmable output differential voltage by changing the multipliers of MOSFETs in a differential pair and resistance with digital codes. Simulation results demonstrate that the proposed DBGR can generate a 25- to 200-mV reference voltage with a 25-mV step within a ±0.7% temperature inaccuracy in a range from −20 to 100°C. The power was 87 nW. A Monte Carlo simulation showed that the coefficient of the variation in the reference was within 1.1%.

The use of compressed sensing (CS) to achieve low-power consumptions in electroencephalogram (EEG) mea-surement devices has attracted considerable research interest. However, a signal processing issue in utilizing CS is the trade- off between the compression ratio (CR), reconstruction accuracy, and reconstruction time. In this study, we developed a method that resulted in a shortened reconstruction time and a high reconstruction accuracy with a high CR by utilizing selected EEG signals. When EEG signals were sorted using the mean frequency and only the most frequently occurring EEG signals were used in the basis matrix, a compressed EEG signal with an original time length of 1 s could be recovered in only approximately 26 ms, and an average normalized mean square error of 0.11 was achieved at a CR of 5.

The realization of a compact wireless electroencephalogram (EEG) measurement device that can be used in daily life without concern for power consumption has garnered considerable attention. Thus, wireless EEG measurement devices with energy harvesting have been proposed, but there have been issues with harvester size and power output. In this study, we proposed and implemented a wireless EEG measurement device using compressed sensing, utilizing random undersampling and only a$40\ \text{mm}\times 40\ \text{mm}$small thermoelectric generator (TEG) as the power source. The results of the 4x compression experiment revealed a reduction in the power of the microcontroller from$345\ \mu\mathrm{W}$to$97\ \mu\mathrm{W}$at 3.3 V. This implies that a wireless EEG measurement device can operate well with a small TEG, even though the reconstructed signal is not inferior to the original signal, in which the average normalized mean square error is approximately 0.24.

Low-voltage charge pump (CP) and its dedicated multi-stage driver (DRV) for sub-50-mV energy harvesting are proposed. The proposed DRV utilizes the output voltages of each CP to efficiently boost the control clock signals. The boosted clock signals are used as switching signals for each CP and DRV to turn switch transistors on and off. Moreover, reset transistors are added to the DRV to ensure an adequate non-overlapping period between switching signals. Simulated results demonstrated that (i) the proposed DRV can generate boosted clock signals of 712.6 mV from input voltage of 100 mV and (ii) the multi-stage CP can generate output voltage of 702.5-mV. Peak efficiency of the CP is 42.9%. The proposed CP and DRV can operate at extremely low voltage of 41 mV.

An analytical study of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for ultra-low voltage energy harvesting is presented. Because the output impedance of the VBC plays an important role in the VBC's performance, we developed an analytical model to achieve a highly efficient VBC. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance Cf, and load capacitance CL. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful to compare the relative merits of different types of multi-stage SC VBCs.

This paper proposes an ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. The proposed active diode consists of a MOS switch and hysteresis common gate comparator, which eliminates unwanted ripple and noise voltages. The hysteresis comparator controls the MOS switch to turn ON or OFF, depending on the input and output voltages. The hysteresis voltages of the comparator can be controlled by the current flowing in the comparator. Simulation results demonstrated that the hysteresis comparator has a -27 and 25 mV hysteresis voltages and the active diode using the hysteresis comparator eliminates unwanted ripple voltage.

We propose a sub-1-μs start-up time, fully integrated 32-MHz relaxation oscillator (ROSC) for intermittent VLSI systems. Our proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. The measurement results demonstrated that the ROSC achieved sub-1-μs start-up time and generated stable output frequency of 32.6 MHz. Measured line regulation, temperature coefficient, and variation coefficient in 10 samples were ±0.69, ±0.38, and 0.62%, respectively.

In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low power real-time clock (RTC) applications. The proposed ROSC is based on a conventional ROSC and modified to be area-efficient circuit configuration, without using resistors. The proposed ROSC consists of a bias current source, proportional to absolute temperature (PTAT) voltage source, current mode ROSC, shunt regulator, and output logic circuit. The PTAT voltage source and shut regulator are used to compensate for the temperature characteristics of the ROSC. By implementing our proposed ROSC in a 65-nm CMOS process, the area was 0.022 mm2. Simulated results demonstrated that our proposed ROSC generates 32.5-kHz clock frequency and achieves ultra-low power dissipation of 271 nW. The temperature and voltage dependences of the oscillation frequency were 138ppm/°C and 13.9ppm/mV, respectively. Monte Carlo statistical simulations showed that the mean, standard deviation, and the coefficient of variation are 32.3 kHz, 0.6 kHz, and 1.9%, respectively.

This paper proposes a mm3-class dual-use near-field antenna that can be used for both magnetic-field based communication and electrical-field based distance sensing. The proposed antenna consists of two spiral coils, and they are used as a coil antenna in communication mode and signal electrodes in distance sensing mode. We evaluated the performance of the communication mode with a prototype antenna. The measured S21 is −8.3 dB to −45.1 dB in the range from 6 mm to 24 mm, which is highly correlated to 3D full-wave electromagnetic simulation. With this antenna, we performed BER evaluation with commercial transceiver boards showing that the proposed antenna could be used for ASK/OOK signaling. We also confirmed that the proposed antenna could be used for cm-scale node-to-node distance sensing through capacitive coupling.

We propose a fully integrated 3-terminal voltage converter with a maximum power point tracking (MPPT) circuit for ultra-low voltage energy harvesting. The MPPT circuit dissipates nano-watt power to extract maximum output power. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input voltage of 0.21 V.

In this paper, we propose a low-power level shifter (LS) capable of converting extremely low-input voltage into high-output voltage. The proposed LS consists of a pre-amplifier with a logic error correction circuit and an output latch stage. The pre-amplifier generates complementary amplified signals, and the latch stage converts them into full-swing output signals. Simulated results demonstrated that the proposed LS in a 0.18-μm CMOS process can convert a 0.19-V input into 1.8-V output correctly. The energy and the delay time of the proposed LS were 0.24 pJ and 21.4 ns when the low supply voltage, high supply voltage, and the input pulse frequency, were 0.4, 1.8 V, and 100 kHz, respectively.

A low-power current reference circuit was developed in a 0.35-μm standard CMOS process. The proposed circuit utilizes an offset-voltage generation subcircuit consisting of sub-threshold MOS resistor ladder and generates temperature compensated reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current, and that the total power dissipation was 586 nW. The temperature coefficient of the reference current can be kept small within 523ppm/°C in a temperature range from -20 to 100°C.

We propose the use of a super-resolution (SR) technique for thermographies. This system captures several thermal images for a reconstruction-based SR. However, it does not require the subpixel registration required by conventional SRs. In this system, a pair of a low-resolution thermal image and a high-resolution visible image is captured synchronously. While the thermal images are used as source data for SR, the visible images are used for pixel registrations. Because the resolution of the visible images from CCD sensors is over 4 times higher than that of the thermal images, a simple pixel registration on the former is equivalent to a precise subpixel registration on the latter. Thus, we can reconstruct a high quality thermogram, without the need for a complex subpixel registration technique. Experimental results demonstrate that a pair of a thermographic camera with only 8×8 pixels and a visible CCD camera with 320 × 240 pixels generates a thermogram with 32 × 32 pixels. This fact means that a pair of a low cost thermographic camera and a standard CCD camera provides high-quality thermography.

An ultra-low power CMOS voltage reference circuit has been fabricated in a 0.35-μm standard CMOS process. The circuit generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference voltage of 745 mV on average. The temperature coefficient and line sensitivity of the circuit were 7 ppm/°C and 20 ppm/V, respectively. The power supply rejection ratio (PSRR) was −45 dB at 100 Hz. The circuit consists of subthreshold MOSFETs with a low-power dissipation of 0.3 μW or less and a 1.5-V power supply. Because the circuit generates a reference voltage based on threshold voltage of a MOSFET in an LSI chip, it can be used as an on-chip process monitoring circuit and as a part of the on-chip process compensation circuit systems.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-mum standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

We designed a simple neural segmentation model that is suitable for analog circuit implementation. The model consists of excitable neural oscillators and adaptive synapses, where the learning is governed by a symmetric spike-timing dependent plasticity (STDP). We numerically demonstrate basic operations of the proposed model as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE).

A floating millivolt reference circuit to generate a PTAT current was developed by using MOSFETs operated in the subthreshold region. The circuit generates a floating voltage of about 10 mV. The variations in the reference are ±2.7 % in a temperature range from -20 to 100 °C. The accuracy of the reference circuit can be improved to ±0.3 % with a correction technique using a curvature-correction circuit. The total power consumption of the circuit was 4.6μW at 100 °C.

We propose an analog current-mode central pattern generator (CPG). Our circuit is based on the neural oscillator proposed by Matsuoka, well known as a building block for constructing a robot locomotion controller. We modified the Matsuoka's oscillator to be suitable for analog current-mode implementation, and implemented it as an analog integrated circuit with current-mode low-pass filters. The oscillator circuit operates in the subthreshold region under the low-supply voltages, and thus low power consumption can be expected. We constructed a CPG circuit with four oscillator circuits. Through SPICE simulations, we confirmed that the CPG circuit generates stable phase-locked oscillation corresponding to typical locomotion of patterns of animals, and that the amplitude and frequency of the oscillation can be controlled by tuning bias currents over a wide range.

A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing synapses. The results of the operations are evaluated by both experiments and simulation program with integrated circuit emphasis (SPICE).

A parallel computer Cenju-4 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor and designed to be scalable up to 1024 nodes. For scalability, Cenju-4 adopts a bit-pattern directory. This scheme enables more precise representation than other imprecise schemes, such as a coarse vector scheme. Cenju-4 utilizes multicast and gathering functions of the network for delivering invalidation request messages and for collecting replies. This enables store access latency to be scalable, even when the block is shared among all nodes. Cenju-4 also prevents starvation and deadlock by queuing certain types of messages in the main memory. This enables a full solution to the starvation problem with centralized directory scheme, and to the deadlock problem with one physical or virtual network. The buffer sizes required for queuing messages at each node are only 32K bytes and two 64K bytes on a 2024-node system. In this paper, we present the design of the DSM architecture and some performance results.