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Samuel Peretz

dblp:27/4826 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 87% Distributed systems · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › routing algorithms
circuit-switched routing
0.011994
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks · ISCA 1994
Interconnection networks and networks-on-chip
router architecture
0.011994
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks · ISCA 1994
Distributed systems
fault tolerance
0.011994
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks · ISCA 1994

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1994 METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks
abstract
The Multipath Enhanced Transit Router Organization (METRO) is a flexible routing architecture for high-performance, tightly-coupled, multiprocessors and routing hubs. A METRO router is a dilated crossbar routing component supporting half-duplex bidirectional, pipelined, circuit-switched connections. Each METRO router is self-routing and supports dynamic message traffic. The routers works in conjunction with source-responsible network interfaces to achieve reliable end-to-end data transmission in the presence of heavy network congestion and dynamic faults. METRO separates the fundamental architectural characteristics from implementation parameters. Simplicity of routing function coupled with freedom in the implementation parameters allows METRO implementations to fully exploit available technology to achieve low-latency and high-bandwidth. We illustrate the effects of this implementation freedom by summarizing the performance which various METRO configurations can extract from some modern CMOS technologies. METROJR-ORBIT, a minimal instance of the METRO architecture constructed in a 1.2 /spl mu/ gate-array technology, is included.>
Fred Chong, Henry Minsky, André DeHon, Matthew E. Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.
ISCA5