Ken Ishikawa

dblp:27/581 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 33% Parallel and multicore computing · 33% Storage systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprogramming
microprogrammable processor
0.011982
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions · IEEE Trans. Computers 1982
Parallel and multicore computing
multiprocessor system
0.011982
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions · IEEE Trans. Computers 1982
Storage systems
nonnumeric processing
0.011982
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions · IEEE Trans. Computers 1982

Methods — techniques the papers use, named apart from their topics

firmware architecture · 0.0
YearPublicationVenuePosition
1982 A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions
abstract
A two-level microprogrammed multiprocessor system, MUNAP, along with its support software has been developed as a research vehicle for solving nonnumeric and associated problems. The MUNAP system provides highly parallel and distributed functions for nonnumeric processing, such as variable length word addressing, data permutation at the microprogram level, and bit operation and field handling at the multinanoprogram level. To control these functions efficiently, a 28-bit microinstruction simultaneously drives several nanoprogram streams of 40-bit nanoinstructions in the four 16-bit processor units. This scheme not only provides the ability to organize a number of modular processing elements into a single, parallel processable computer system, but also allows MUNAP to change its architecture at the firmware level.
Takanobu Baba, Ken Ishikawa, Kenzo Okuda
IEEE Trans. Computers2