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Mohsen Saneei

dblp:27/6164 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2006
0000-0002-2722-6064ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 70% Energy-efficient computing · 23% Processor architecture and microarchitecture · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.112005
Sign bit reduction encoding for low power applications · DAC 2005
Integrated circuit design
low-power circuit design		 0.112005
Sign bit reduction encoding for low power applications · DAC 2005
Integrated circuit design › digital circuit design › arithmetic circuit design
multiplier design		 0.112005
Sign bit reduction encoding for low power applications · DAC 2005
Energy-efficient computing › dynamic power reduction
switching activity reduction		 0.112005
Sign bit reduction encoding for low power applications · DAC 2005
Processor architecture and microarchitecture › microprocessor design › processor core design › datapath design
data bus encoding		 0.012005
Sign bit reduction encoding for low power applications · DAC 2005

Methods — techniques the papers use, named apart from their topics

sign bit reduction encoding · 0.1
YearPublicationVenuePosition
2006 Low-power and low-latency cluster topology for local traffic NoCs
abstract
In this paper, we introduce a topology for network on chips that is named cluster-mesh (CM) topology. This architecture reduces dynamic and static power consumption in NoCs and can reduce latency of communications in low traffic or local traffic applications. With cluster-mesh topology, area reduction in routers is about 44% and in links we can save more than 50% in area too. The dynamic power in this architecture is reduced more than 20%. The idea of clustering may be applied to some other topologies such as Torus and Octagon
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
 ISCAS1
2005 Sign bit reduction encoding for low power applications
abstract
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of some digital systems such as digital filters based on CMOS logic system can be reduced considerably compared to those based on 2's complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by this scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2's complement implementation. For 16-bit random data, this scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads up to 14.5% switching reduction on average.
Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
 DAC1