EDBT 2026 Demo / reviewers in the wild / expert
Terence B. Hook
dblp:27/6337
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
layout parameter extraction |
0.0 | 1 | 1992 | Automatic extraction of circuit models from layout artwork for a BiCMOS technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation
physical design |
0.0 | 1 | 1992 | Automatic extraction of circuit models from layout artwork for a BiCMOS technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1992 | Automatic extraction of circuit models from layout artwork for a BiCMOS technology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
resistor mesh generation · 0.0parasitic capacitance extraction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Enchanced multi-threshold (MTCMOS) circuits using variable well biasabstractArticle Share on Enchanced multi-threshold (MTCMOS) circuits using variable well bias Authors: Stephen V. Kosonocky IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Mike Immediato IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Peter Cottrell IBM Microelectronics, Burlington, VT IBM Microelectronics, Burlington, VTView Profile , Terence Hook IBM Microelectronics, Burlington, VT IBM Microelectronics, Burlington, VTView Profile , Randy Mann IBM Microelectronics, Burlington, VT IBM Microelectronics, Burlington, VTView Profile , Jeff Brown IBM Microelectronics, Burlington, VT IBM Microelectronics, Burlington, VTView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 165–169https://doi.org/10.1145/383082.383125Online:06 August 2001Publication History 22citation492DownloadsMetricsTotal Citations22Total Downloads492Last 12 Months5Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown |
ISLPED | 4 |
| 1992 | Automatic extraction of circuit models from layout artwork for a BiCMOS technologyabstractAn approach to modeling BiCMOS circuitry in which a simulation card desk is produced directly from the circuit layout artwork is described. The cards contain sufficient information about the device dimensions and net interconnections to form a complete circuit model. The approach allows extensive integration of the devices into an optimal layout and includes the interaction of a PFET and an NPN built in the same well. The active device menu includes NFETs, PFETs, NPNs, and resistors. Parasitic capacitances associated with the source and drain diffusions are calculated and a resistor mesh in the subcollector is created. The individual steps leading to the formation of the circuit model are described, and examples of bipolars and BiCMOS circuits are shown.> Terence B. Hook |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |