Demo Data from EDBT 2026 / reviewers in the wild / expert
Steven J. Wallach
dblp:27/6450
· DBLP profile ↗
6ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
High-performance computing · 49% Parallel and multicore computing · 37% Performance modeling and evaluation · 15% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 67% Operating systems · 33% |
Topics — the 5 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing
supercomputing |
0.0 | 1 | 1995 | Goldilocks and the Three Bears Confront the Future of Supercomputing · SC 1995 |
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor |
0.0 | 1 | 1988 | The convex C240 architecture · SC 1988 |
Parallel and multicore computing › multiprocessor system
tightly-coupled multiprocessor |
0.0 | 1 | 1988 | The convex C240 architecture · SC 1988 |
Compilers and program optimization › parallelization
automatic parallelization |
0.0 | 1 | 1988 | The convex C240 architecture · SC 1988 |
Compilers and program optimization
vectorization |
0.0 | 1 | 1988 | The convex C240 architecture · SC 1988 |
Methods — techniques the papers use, named apart from their topics
automatic vectorization · 0.0automatic parallelization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Issues on the architecture and the design of distributed shared memory systemsabstractDistributed shared memory (DSM) systems could overcome major obstacles of the widespread use of distributed-memory multiprocessors, while retaining the attractive features of low cost and good scalability common to distributed-memory machines. A DSM system allows a natural and portable programming model on distributed-memory machines, making it possible to construct a relatively inexpensive and scalable parallel system on which programmers can develop parallel application codes. Due to its potential advantages, DSM has received increasing attention. In this panel, challenges in building efficient DSM systems for a wide range of applications are addressed and discussed. Nian-Feng Tzeng, Steven J. Wallach |
ICCD | 2 |
| 1995 | Automatic Self-Allocating Threads (ASAT) on the Convex Exemplar
Charles R. Severance, Richard J. Enbody, Steven J. Wallach, Brad Funkhouser |
ICPP (1) | 3 |
| 1995 | Goldilocks and the Three Bears Confront the Future of SupercomputingabstractNo abstract available. Robert Borchers, Burton J. Smith, Steven J. Wallach |
SC | 4 |
| 1994 | Parallel Processing: What Have We Done Wrong?abstractParallel processing has been a subject of extensive research for over 20 years, especially in the last 10 years, with many commercial parallel machines becoming available, from small scale parallel machines to massively parallel machines. At one time, it was claimed that parallel machines will become the mainstream computers. However, more recently, some parallel computer vendors have gone out of business and some others are struggling. Some pessimists even claimed that this is a dying field. So, what’s wrong? Five distinguished panelists are invited to share their views on this issue. The panelists are also expected to address what could be done and could be done in order to make parallel computers truly mainstream computers. Panelists Lionel M. Ni, Kuo-Wei Wu, Ken Kennedy, Howard Jay Siegel, George Spix, Steven J. Wallach, Hans P. Zima |
ICPADS | 6 |
| 1994 | Towards Teraflop ComputingabstractHigh-performance computing is moving towards commercially available teraflop platforms. The various attributes of this movement will be examined. Chip technology, interconnect, programming model, as well as data management will be explored. Future trends as they relate to these features will also be analyzed. Steven J. Wallach |
ICPADS | 1 |
| 1988 | The convex C240 architectureabstractA description is given of the C240, a tightly coupled, shared memory, parallel multiprocessor that supports up to 40-ns ECL/CMOS Cray-like processors. It is managed by a fully semaphored Unix operating system and can support up to 4 Gb of directly addressable physical memory. Convex proprietary compiler technology provides automatic vectorization and parallelization for Fortran, C and Ada. The allocation of parallel threads to physical processors is managed by ASAP (automatic self-allocating processors), which dynamically allocates and deallocates parallel threads to the processors.> M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach |
SC | 4 |