The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures have become very complex and difficult to optimize with automatic clock tree synthesis (CTS) tools. In advanced process nodes, CTS becomes even more challenging due to on-chip variation (OCV) effects. In this paper, we present a new CTS methodology that optimizes clock logic cell placements and buffer insertions in the top level of a clock tree. We formulate the top-level clock tree optimization problem as a linear program that minimizes a weighted sum of timing slacks, clock uncertainty and wirelength. Experimental results in a commercial 28nm FDSOI technology show that our method can improve post-CTS worst negative slack across all modes/corners by up to 320ps compared to a leading commercial provider's CTS flow.

This paper presents a scheme called PrePack for suppressing the channel traffic between simulator and accelerator in the accelerator-based hardware/software co-emulation where the accelerator models some register transfer level (RTL) subblocks while the simulator runs transaction-level modeling (TLM) of the remaining part of the design under verification (DUV). With the conventional simulation accelerator, a cycle consisting of a pair of evaluations of simulator and accelerator occurs at every valid simulation time, which results in poor simulation performance due to the overhead of simulator–accelerator channel access, often accounting for more than 99% of total channel traffic time (total channel traffic time consists of channel-access time for arbitration/protocol exchange and pure data/signal transmission time). The overhead due to channel access can be reduced by merging as many channel transactions on the channel as possible into a single burst traffic, which is achieved in this paper by “prediction and rollback.” In the proposed “prediction and rollback” scheme, one of the two verification domains, i.e., software simulation and hardware acceleration, leads the other, while the leading domain predicts the states of the lagging domain. Therefore, the evaluation of simulator and accelerator no longer need to alternate at every simulation cycle. Under an ideal condition with 100% prediction accuracy, PrePack has shown a 15$times$speedup compared to the conventional scheme. When applied to advanced encryption standard (AES) and joint photographic experts group (JPEG) example systems, PrePack showed performance gains of 8.7 and 2.9, respectively.

This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.

The paper presents a scheme for efficient channel usage between simulator and accelerator, where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs a transaction-level model of the remaining part of the whole chip being verified. With conventional simulation, accelerator evaluations of simulator and accelerator alternate at every valid simulation time, which results in poor simulation performance due to the startup overhead of simulator-accelerator channel access. The startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic. We propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on 'prediction and rollback'. Under ideal conditions with 100% prediction accuracy, the proposed method shows a performance gain of 1500% compared to the conventional one.