A previously developed passively operating transmission capable of switching its reduction ratio in response to load torque was further developed into a non-contact load-responsive transmission. The reduction ratio is switched by a non-contact magnetic clutch that responds to the load torque using a passive magnetic mechanism without any accessory actuators, sensors, electronics or power supplies. The absence of mechanical friction at the non-contact magnetic clutch resolves the problems concerning the wear and maintenance, shock while switching the clutch is greatly reduced and the actuator is protected from overloads by slippage at the magnetic clutch. This non-contact load-responsive transmission reduces the power, size and weight of the mechanical system and improves its safety and agility since a variant load can be actuated efficiently using a minimal actuator. This paper describes the structure and the operation of the non-contact load-responsive transmission and reports on the characteristics of an experimentally evaluated prototype transmission.

This paper presents personal networks, which integrate a VPN and the per-VPN execution environments of the hosts included in the VPN. The key point is that each execution environment called a portspace is bound to only one VPN, i.e., single-homed. Using this feature of portspaces, personal networks address several problems at multi-homed hosts that use multiple VPNs. Information flow is separated by personal networks so that it is not mixed at multi-homed hosts. IP addressing in a personal network is independent of the other personal networks, even the base network, and therefore does not conflict with those of other networks at multi-homed hosts. In addition, personal networks provide facilities for easy bootstrapping so that the end-users can construct such isolated networks easily. Inheritance of portspaces supports the creation of new portspaces based on existing portspaces. Self-construction of personal networks enables end-users to construct personal networks without help from the base network.

We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms were developed based on a single local optimization function, called the sequential cut line objective function. Our algorithm incorporates global objective functions into this traditional framework of min-cut placement. In particular, we introduce a new global objective function based on the congestions for cut lines and use it for the selection of their sequence. We also use the total cut value objective function in the determination of the sizes and connectivities of clusters that are to be used in the early stages of min-cut partitioning. The incorporation of such global objective functions yields additional reductions of wire congestions in the entire as well as local chip areas. With the automatic selection and use of such clusters and a cut line sequence, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips of 1.5 K to 150 K raw gates.>

We introduce a new model for over-the-cell channel routing with three layers. The model consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively. We formulate the problem of over-the-cell routing as that of channel routing with additional constraints. Based on this formulation, we present an efficient over-the-cell routing algorithm that attempts to minimize the sum of channel densities of the trunks that remain in the channel. The effectiveness of our model and algorithm is demonstrated by our experimental results on industrial sea-of-gates array chips and a well-known benchmark circuit.>

The authors propose an approach to an over-the-cell channel routing problem using a model that consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively, The problem is decomposed into two phases: over-the-cell routing and channel routing. The authors formulate the problem in the first phase as that of channel routing with additional constraints. Based on this formulation, they present an efficient over-the-cell routing algorithm. The effectiveness of the approach is demonstrated by experimental results on sea-of-gates array chips.>

This paper presents a new min-cut placement algorithm for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays called GALOP [1] and has been successfully applied to clock skew control of an ECL 12K-gate gate array.

This paper provides an outline, together with application results and functional improvements, of the symbolic layout system MGX. MGX was developed to support the layout design of the functional blocks of microprocessors for MOS technology. The point considered the most important when we started developing MGX is reducing design time without much waste of silicon area. In order to achieve this goal, a layout style in MGX in which all symbolic layout elements are on movable grid points and which has an orderly structure is adopted, and the fast compaction algorithm is selected. Another consideration for the system is to support the whole LSI layout process. Using MGX, a 16-bit microcontroller chip was successfully designed. MGX offered high transistor packing density and high productivity of the layout design. The experience with this layout design has shown that another goal to be achieved in the development of a symbolic layout system is the ability to update designed physical layout patterns with advances in LSI fabrication technology without having to redo the layout. Hence, MGX has been improved so as to deal with various design rules which may become possible with advances in LSI fabrication technology and to give higher transistor packing density. Experimental results show that the transistor packing density of the layout of a D flip-flop which is designed by using MGX increases by approximately 39 percent due to these improvements.

In the masterslice LSI, since the wiring area is fixed, local wiring congestion is likely to occur, which may cause the occurrence of some wiring nets to be unroutable. If the number of grids used in the routing can be accurately predicted before the wire routing, it is possible to reduce greatly the occurrence of wiring nets to be unroutable.

A grid-free channel router (termed GFR) is reported. GFR does not employ grid lines and can obtain better results than the fixed-grid method. Additionally, GFR has several optional functions, such as constraint loop breaking, total branch length minimization, constraint chain cutting and layer changing. The algorithms of these functions are outlined and results obtained by using them are presented.

It is shown that there exists an algorithm to determine whether or not a given multivalued variable-length encoding, that is, a variable-length code system in which more than one codeword may correspond to one source symbol, is uniquely decipherable. The proof is given in two steps. The problem is first reduced to a simpler one, that of determining the inclusion relation between two rather simple languages, a regular set and a language defined by two shortening homomorphisms. Then a concrete decision procedure is given for this simpler problem. Several further observations are made, including a conjectured decision method for the finite-delay property.