Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ting-Ying Chien

dblp:27/7240 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD › flash memory › flash storage
bit-alterable flash memory
0.612022
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory · IEEE Trans. Computers 2022
Storage systems › flash and SSD
flash memory
0.612022
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory · IEEE Trans. Computers 2022
Storage systems › flash and SSD › flash memory management
garbage collection
0.612022
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory · IEEE Trans. Computers 2022
Storage systems › flash and SSD › flash memory management
wear leveling
0.612022
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory · IEEE Trans. Computers 2022
Storage systems › storage reliability › durability
flash lifetime
0.212022
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory · IEEE Trans. Computers 2022

Methods — techniques the papers use, named apart from their topics

duo-phase data management · 0.6
YearPublicationVenuePosition
2022 Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory
abstract
Bit-alterable flash memory is a cutting-edge technology that enables a novel operation, called page-level erase operation, to erase a flash page within a block arbitrarily. Though the page-level erase operation can ease the overhead of the live-page copying during a garbage collection process, it also introduces a new wear-leveling problem. In such the problem, flash pages within the same block will receive different program/erase (P/E) cycles during runtime. Some specific pages storing hot data will be worn out soon; therefore, the lifespan of the bit-alterable flash memory will be short due to the uneven worn out of flash pages. Consequently, it becomes a critical issue with the bit-alterable flash memory, and the state-of-art wear-leveling designs cannot resolve this problem. For tackling the problem, this study presents a duo-phase data management scheme considering the page-level wear-leveling issue. The duo-phase mechanism simultaneously cares about page- and block-level wear-leveling issues. On the page-level wear-leveling problem, the duo-phase scheme identifies hot flash pages via the few bits and softly restricts the hot flash page to store hot data. On the other hand, our proposed mechanism also figures out the solution to minimize the number of copied live pages for the block-level wear-leveling issue.
Tseng-Yi Chen, Shao-Hung Chi, Ming-Chang Yang, Ting-Ying Chien
IEEE Trans. Computers4