This paper proposes an architecture for accomplishing transport protocol processing at Gbps rates. The limitations of currently used transport protocols have been analyzed extensively in recent literature. Several benchmark studies have established the achievable throughput of ISO TP4 and TCP to be in the low Mbps range; several new protocols and implementation techniques have been proposed to achieve 100 Mbps and higher throughput rates. We briefly review some of these protocols and establish the need for a radically different approach to meet our objective. An estimate of the aggregate processing power required for Gbps throughput is developed. It is proposed that a cost effective and practical solution to the processing requirements could be based on a multi-processor system. The opportunities for parallel processing in a typical transport protocol are examined. Several alternate parallel processing approaches are examined and arguments are advanced for selecting a favored approach. A corresponding parallel processing architecture is described. Data structures used to preserve packet ordering and techniques for reducing contention in a multi-processing environment are discussed. An implementation methodology for conventional transport protocols (e.g. TP4) is outlined. Some suggestions are made for improving efficiency by making modifications to the protocol that do not compromise functionality. The performance achievable with this modified architecture is analyzed and some suggestions for further work are presented.

A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.