!Unmanned Aerial Vehicle (UAV or drone) classification is critical for surveillance, enabling the identification and distinction of drones for military, civilian, and other security applications. Although deep learning models trained on radio frequency (RF) signals show promise for drone classification, they often lack robustness in real-world and variable-noise environments. This limitation stems from their reliance on static feature fusion strategies, which cannot adaptively prioritize the most discriminative time-frequency information. To address this limitation, we propose a multi-scale convolutional neural network (MS-CNN) enhanced with a novel attention mechanism. Specifically, our model dynamically learns to weight multi-scale features extracted from Short-Time Fourier Transform (STFT) representations of RF signals, enabling it to focus on the most relevant signal characteristics under varying noise levels. Trained on a mixed signal-to-noise ratio (SNR) dataset augmented with synthetic additive white gaussian noise (AWGN), the MS-CNN learns inherent robustness without requiring explicit noise-specific tuning. When evaluated on the large-scale DroneRFa dataset, which comprises 24 drone classes and one noise class under controlled AWGN across an SNR range of -20 dB to 10 dB, our model achieves a peak accuracy of 99.04% at 0 dB SNR and consistently outperforms existing benchmark methods.

Masking countermeasures are robust solutions applied to cryptographic devices to improve their side-channel analysis resistance. Implementing substitution boxes (S-boxes) and using an efficient mask scheme are essential for improving security in modern ciphers. Consequently, this paper proposes an improved tower field mask scheme with an affine transformation-based dynamic S-box. The approach resists both Correlation Power Analysis attacks with Hamming Weight and Hamming Distance models, even when employing up to two million power traces. The measurement-to-disclosure improvement for the extracted key byte is at least 158× higher than the previous scheme, while our hardware overhead is around 1.04×. Furthermore, the proposal enhances the devices’ resistance to recent Deep-Learning Side-Channel Analyses.

The Mixed-Mode Clock Manager (MMCM) is a primitive in Xilinx FPGAs that is designed for generating a wide range of output clock frequencies by utilizing a fixed input clock signal. It has been applied to numerous cryptographic devices to improve their side-channel attack resistance. This paper proposes an efficient hiding countermeasure by using the MMCM in spread spectrum mode. In our suggested architecture, the hardware implementation is given by random dynamic frequency-hopping signals. We could achieve better effectiveness in the occupied bandwidth metrics and found 223 available parameter sets, which is significantly smaller than using 219k distinct sets in a previous study, namely a random dynamic frequency scaling countermeasure. The experimental results indicate that a recent deep learning-based leakage assessment requires nearly one million traces to detect leakage points, whereas the well-known t-test methodology cannot detect any information leakage in five million measurements. Furthermore, this countermeasure is capable of withstanding both conventional and sliding window-based Correlation Power Analysis attacks, despite utilizing up to five million power traces.

Side-channel attacks have emerged as the predominant approach for exploiting the weaknesses of cryptographic equipment. Therefore, it is becoming increasingly necessary to prioritize countermeasures that can improve the security level of these implementations. A Mixed-Mode Clock Manager (MMCM) primitive has been utilized in several time-based hiding countermeasures against side-channel attacks. However, they cannot be applied to ASIC implementations because the MMCM is a Xilinx primitive. Consequently, this paper proposes a hybrid dynamic Gold code-based solution to generate multiple different frequencies. The countermeasure combines a pair of preferred polynomials with one ring oscillator, so it is suitable for both FPGA and ASIC designs. The hardware overhead of our suggested architecture is 1.007× and 1.009× in terms of slice LUTs and registers, respectively. The total area cost of the circuit on the CMOS 0.18 um process is 398,835 square micrometers, representing a 1.004x increase compared to the unprotected case. Moreover, the approach is resistant to both standard and sliding window-based Correlation Power Analysis attacks, even when employing UP to one million power traces.

The integration of radar and communication systems in 6G networks has led to a significant challenge of spectrum congestion. To address this issue, we propose a deep learning-based method for efficient waveform-based signal classification. Our method is designed to handle large and impaired radar and communication signals, and is crucial for the implementation of resource-limited cognitive radio-enabled Internet-of-Things (CR-IoT) devices. We introduce WaveNet, a cost-efficient deep convolutional neural network that can aptly learn underlying radio features from time-frequency images transformed by a smooth pseudo Wigner-Ville distribution. WaveNet incorporates several innovative modules, including cost-efficient feature awareness, which integrates two well-designed structural blocks: grouped-of-kernel-wise residual connections and dual asymmetric channel attention. These enhancements significantly reduce network size without compromising classification accuracy. Based on various simulations experimented on an impaired signal dataset containing eight radar and communication waveform types, the results demonstrate the effectiveness and robustness of WaveNet, achieving an overall classification accuracy of 92.02%. Compared to the current state-of-the-art deep models, WaveNet has the lowest architectural complexity, with a network size five times smaller, while still outperforming them by approximately 0.5 – 1.69%. Consequently, WaveNet emerges as a valuable solution for waveform classification in integrated radar-communication 6G systems.

Nowadays, cryptographic algorithms are widely used to build safety mechanisms for specific objects in security services. Nevertheless, these algorithms are implemented in the hardware or software of the physical devices. Consequently, attackers will exploit physical information leakages, such as the device’s power consumption, and use them to get secret keys. The correlation power analysis (CPA) attack is a powerful and efficient cryptographic technique. The evaluation method, however, takes time because many traces are necessary to overcome designs protected by different countermeasures. Therefore, this article proposes a new technique to reduce the computation time by extracting the point of interest (POI) with an interpolation method. The proposal uses the local extreme value and two adjacent samples around it to interpolate the actual peak amplitude. Compared to the conventional CPA, the execution time in our solution is decreased by approximately$9.55\times $, with only 53.32% of the given power traces used for attacking the masking design. Moreover, this technique can deal with the public desynchronized ASCAD database and has better results than recent alignment preprocessing methods. We apply the proposal in the preprocessing step before performing the previously non-profiled deep learning-based attacks. Our suggestion requires only 5000 traces, while the reported attacks fail or require more traces to recover the correct subkey.

Side-channel analysis attacks have become the primary method for exploiting the vulnerabilities of cryptographic devices. Therefore, focusing on countermeasures to enhance the security level of these implementations evolves even more urgently. This article proposes a time-based hiding countermeasure by using spread-spectrum signals. In our RISC-V system on chip (SoC), cryptographic accelerators are given by random dynamic frequency-hopping signals. We found 223 available parameter sets for a Xilinx Mixed-Mode Clock Manage primitive in spread spectrum mode and achieved better effectiveness in the occupied bandwidth (OBW) metric. The mixed mode clock managers (MMCMs) output signal and the range of frequencies within the spread will be changed randomly, resulting in multiple clocks for individual encryption. The effectiveness of this proposal is demonstrated by conducting realistic side-channel attacks (SCAs) and state-of-the-art leakage assessment methodologies on the well-known data encryption standard, i.e., the Advanced Encryption Standard (AES) accelerator. Even though we used up to five million power traces, the test results show that our defense can stand up to a regular correlation power analysis (CPA) attack as well as alignment preprocessing methods, like CPA attacks that use a sliding window or an amplitude peak location algorithm. Furthermore, the t-test methodology cannot detect any first-order information leakage in five million traces; meanwhile, the deep learning leakage assessment (DLLA) requires nearly one million power traces in the training test to detect leakage points.

Research on side-channel attacks has recently made a lot of progress, and one of the most potential solutions is a power analysis attack. Thus, focusing on countermeasures to improve the security level of cryptographic devices is a matter of concern. This paper proposes a time-based hiding countermeasure by using a dynamic Gold code-based chaotic clock. In our work, 36.95% (143 out of 387) of parameter sets that pass two standard statistical test suites can be used to reconfigure the Gold code generator's initial vector. The experimental results demonstrate that our countermeasure helped to harden the targeted Advanced Encryption Standard against several alignment pre-processing methods. When compared to the Random Dynamic Frequency Scaling countermeasure, the number of traces required to reveal the secret key must be increased by three times, but the overhead is approximately four times lower.

Abstract In modern embedded systems, security issues including side‐channel attacks (SCAs) are becoming of paramount importance since the embedded devices are ubiquitous in many categories of consumer electronics. Recently, deep learning (DL) has been introduced as a new promising approach for profiled and non‐profiled SCAs. This paper proposes and evaluates the applications of different DL techniques including the Convolutional Neural Network and the multilayer perceptron models for non‐profiled attacks on the AES‐128 encryption implementation. Especially, the proposed network is fine‐tuned with different number of hidden layers, labelling techniques and activation functions. Along with the designed models, a dataset reconstruction and labelling technique for the proposed model has also been performed for solving the high dimension data and imbalanced dataset problem. As a result, the DL based SCA with our reconstructed dataset for different targets of ASCAD, RISC‐V microcontroller, and ChipWhisperer boards has achieved a higher performance of non‐profiled attacks. Specifically, necessary investigations to evaluate the efficiency of the proposed techniques against different SCA countermeasures, such as masking and hiding, have been performed. In addition, the effect of the activation function on the proposed DL models was investigated. The experimental results have clarified that the exponential linear unit function is better than the rectified linear unit in fighting against noise generation‐based hiding countermeasure.

Physical cryptographic devices are vulnerable to side-channel information leakages during operation. They are widely used in software as well as hardware implementations, ranging from microcontrollers and microprocessors to hardware accelerators in System on Chips (SoCs). Nowadays, cryptographic RISC-V SoCs are becoming the most prominent solution compared to the rest. Cryptographic accelerators provide users with a very high level of flexibility and customization of chips suited to specific applications in these systems. First, this research aims to confirm the effectiveness of the Correlation Power Analysis attack on cryptographic SoCs based on three different power consumption models. In each model, the effectiveness of an attack depends on the transition factor, which is a ratio related to different characteristics of the device's power consumption. Then, we focus on modifying the configuration on the SoC and attacking the AES hardware implementation on these designs. The experimental results show that applying the Switching Distance model brings the highest performance. With our suggested range of transition factors, the number of traces needed to find the secret key can be reduced by 13.35% in the best case.

In this demonstration, a real-time auto-exposure Histogram Equalization (HE) video-system is presented. The video histogram is extracted in each frame by the Frequent Items Counter (FIC) core. Based on the HE Transformation Function (HE-TF), the camera exposure value is adjusted to fit the current luminance condition. The proposed system was developed on the VEEK-MT-SoCKit with an FPGA chip of Altera Cyclone V SoC and a 5-Megapixel (5-MP) Charge Coupled Device (CCD). The video resolution is 1280×800. The monitor display rate is at 60Hz while the CCD capture rate is at 24.28Hz to 38.98Hz depend on the exposure value. The histogram, the transformation function, and the camera exposure value are changed in each frame to satisfy the real-time requirement.

Although bitmap index (BI) can surmount complex and multi-dimensional queries, the creation of BI itself is a time-consuming task. Many studies exploit the highly parallel processing capabilities of multi-core CPUs, graphics processing units (GPUs), or field-programmable gate arrays (FPGAs) to overcome this obstacle. This study, on the other hand, proposes a 65-nm silicon-on-thin-buried-oxide (SOTB) hardware accelerator dedicated to BI creation. The fabricated chip could operate at different supply voltages, from 0.45-V to 1.2-V. Concretely, in the active mode with the supply voltage of 1.2-V, this chip was fully operational at 90-MHz and consumed approximately 88.1-pJ/cycle. In the standby mode with the supply voltage of 0.45-V and clock gated, the power consumption was only 476.1-nW. Moreover, when the reverse back-gate bias voltage of -2.5-V is supplied, the standby power sharply dropped to 0.27-nW or approximately 1,763 times. This achievement is vitally essential for the energy-efficient applications, where the performance should be maximized during peak workload hours and the power should be minimized during off-peak time.

We investigate a novel fully digital background calibration technique to mitigate the gain and timing mismatches in Time-Interleaved Analog-to-Digital Converters (TIADCs) for the wideband bandlimited input signal at any Nyquist zones. The correction scheme is simple by subtracting the image signals from the distorted signal. The channel mismatch parameters are estimated based on out-of-band error estimation. Neither an additional reference channel and nor a pilot input are required in calibration. A four-channel 60dB SÒR TIADC operating at 2.7GHz is used in both simulation and experimental implementation to validate the proposed calibration technique. The SNDR improvement is 16dB for a multi-tone input occupied at the third Nyquist band. The calibration method is validated on Altera FPGA DE4 board. In a Hardware-In-the-Loop emulation framework, the synthesized circuit works effectively and utilizes a very little amount of the hardware resource in the FPGA chip.

This paper presents a compact, ultra-low power AES-CCM authenticated encryption IP core for WBANs by combining a low area 8-bit AES encryption core, iterative structure and other optimized circuits. The proposed AES-CCM IP core can be used for the message security at the MAC level, e.g. message encryption and authentication, based on AES forward cipher function with a 128-bit key for counter and cipher block chaining modes of operations. The implementation results show that the proposed AES-CCM IP core achieves a very high resource efficiency and ultra-low power consumption while meeting the requirement of operation speed in WBANs.