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Przemyslaw Szczerbicki

dblp:27/9915 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.112011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation › hardware verification and test
low-power testing
0.112011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation › hardware verification and test
test data compression
0.112011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011

Methods — techniques the papers use, named apart from their topics

deterministic clustering · 0.1cube merging · 0.1continuous flow decompression · 0.1
YearPublicationVenuePosition
2011 Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression
abstract
The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2010 Low power compression of incompatible test cubes
abstract
The paper presents a new power-aware test scheme compatible with a newly proposed test compression environment based on deterministic clustering of test cubes with conflicts. The key contribution is a flexible test application framework that achieves significant reductions in switching activity during scan loading by means of a tri-modal test data decompressor.
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
ITC5