This paper describes an array processor designed for signal processing in radar applications. The processor consists of a large number of microprocessor-based processing elements and is designed to be adaptive in real-time processing requirements. The processing problem has been considered to have a quite specific data organization and data rate which can be exploited in the architectural design. Parallel processing is necessary and a pipelined approach was adopted. A generalized pipeline philosophy is described which leads to a description of the hardware structure. The development of a single level control structure with separate generation of opcodes and addresses is noted.