EDBT 2026 Demo / reviewers in the wild / expert
U. Gyeong Song
dblp:270/3831
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 50% Hardware accelerators and domain-specific architectures · 38% Cloud and datacenter computing · 12% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Bioinformatics and computational biology · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › spatial architecture
dataflow accelerator |
0.4 | 1 | 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data Analysis · ISCA 2020 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.4 | 1 | 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data Analysis · ISCA 2020 |
Bioinformatics and computational biology › genomics
genomic data analysis |
0.1 | 1 | 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data Analysis · ISCA 2020 |
Cloud and datacenter computing › cloud deployment
cloud FPGA deployment |
0.1 | 1 | 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data Analysis · ISCA 2020 |
Reconfigurable computing and FPGAs › cloud FPGA
FPGA-as-a-service |
0.1 | 1 | 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data Analysis · ISCA 2020 |
Methods — techniques the papers use, named apart from their topics
on-chip scratchpad · 0.9non-blocking APIs · 0.9extended SQL · 0.9dataflow architecture · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Genesis: A Hardware Acceleration Framework for Genomic Data AnalysisabstractIn this paper, we describe our vision to accelerate algorithms in the domain of genomic data analysis by proposing a framework called Genesis (genome analysis) that contains an interface and an implementation of a system that processes genomic data efficiently. This framework can be deployed in the cloud and exploit the FPGAs-as-a-service paradigm to provide cost-efficient secondary DNA analysis. We propose conceptualizing genomic reads and associated read attributes as a very large relational database and using extended SQL as a domain-specific language to construct queries that form various data manipulation operations. To accelerate such queries, we design a Genesis hardware library which consists of primitive hardware modules that can be composed to construct a dataflow architecture specialized for those queries. As a proof of concept for the Genesis framework, we present the architecture and the hardware implementation of several genomic analysis stages in the secondary analysis pipeline corresponding to the best known software analysis toolkit, GATK4 workflow proposed by the Broad Institute. We walk through the construction of genomic data analysis operations using a sequence of SQL-style queries and show how Genesis hardware library modules can be utilized to construct the hardware pipelines designed to accelerate such queries. We exploit parallelism and data reuse by utilizing a dataflow architecture along with the use of on-chip scratchpads as well as non-blocking APIs to manage the accelerators, allowing concurrent execution of the accelerator and the host. Our accelerated system deployed on the cloud FPGA performs up to 19.3× better than GATK4 running on a commodity multi-core Xeon server and obtains up to 15× better cost savings. We believe that if a software algorithm can be mapped onto a hardware library to utilize the underlying accelerator(s) using an already-standardized software interface such as SQL, while allowing the efficient mapping of such interface to primitive hardware modules as we have demonstrated here, it will expedite the acceleration of domainspecific algorithms and allow the easy adaptation of algorithm changes. Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee 0001, Seong Hoon Seo, U. Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, Lisa Wu Wills |
ISCA | 6 |