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Jonathan Johnson

dblp:270/3927 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Software engineering, systems software and programming languages · 1Human-computer interaction and ubiquitous computing · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Integrated circuit design · 23%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Machine learning › Efficient and distributed learning
model quantization
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Machine learning › Efficient and distributed learning › model deployment
quantized model deployment
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020
Integrated circuit design
system-on-chip
0.112020
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product · ISCA 2020

Methods — techniques the papers use, named apart from their topics

quantization · 0.9SIMD architecture · 0.9
YearPublicationVenuePosition
2026 TAuC-SoC: A 0.36 mm2 In-Yarn Integrable Tiny Audio Compressor SoC for E-Textile Based Audio Recording Applications
Suprio Bhattacharya, Charlie D. Hess, Omar Faruqe, J. Keith McElveen, Douglas Cairns, Doug Overland, Jonathan Johnson, Daniel S. Truesdell, Benton H. Calhoun
ISCAS7
2021 Multi-Robot Information Gathering Subject to Resource Constraints
abstract
This paper addresses the multi-robot planning problem to generate trajectories for maximum information gathering from an area of interest. To solve this problem, the proposed framework first leverages a Gaussian Mixture Model (GMM) as prior knowledge for modeling informative regions in the target area. Taking samples from the GMM, informative robot paths are then computed that optimize the travel costs subject to energy budgets. Decomposing these paths into waypoints, robot trajectories are planned while respecting kinematic constraints and subsequently replanned online to avoid collisions among themselves. The GMM model is incrementally updated by incorporating the gathered information. We demonstrate that our framework can achieve a significant amount of information gain with the optimal travel distance. We also provide a realistic simulation with a team of mobile robots in a port infrastructure monitoring setting.
Abdullah Al Redwan Newaz, Tauhidul Alam, Joseph Mondello, Jonathan Johnson, Leonardo Bobadilla
RO-MAN4
2020 High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product
abstract
Demand for high performance deep learning (DL) inference in software applications is growing rapidly. DL workloads run on myriad platforms, including general purpose processors (CPU), system-on-chip (SoC) with accelerators, graphics processing units (GPU), and neural processing unit (NPU) addin cards. DL software engineers typically must choose between relatively slow general hardware (e.g., CPUs, SoCs) or relatively expensive, large, power-hungry hardware (e.g., GPUs, NPUs). This paper describes Centaur Technology's Ncore, the industry's first high-performance DL coprocessor technology integrated into an x86 SoC with server-class CPUs. Ncore's 4096 byte-wide SIMD architecture supports INT8, UINT8, INT16, and BF16 datatypes, with 20 tera-operations-per-second compute capability. Ncore shares the SoC ring bus for low-latency communication and work sharing with eight 64-bit x86 cores, offering flexible support for new and evolving models. The x86 SoC platform can further scale out performance via multiple sockets, systems, or third-party PCIe accelerators. Ncore's software stack automatically converts quantized models for Ncore consumption and leverages existing DL frameworks. In MLPerf's Inference v0.5 closed division benchmarks, Ncore achieves 1218 IPS throughput and 1.05ms latency on ResNet-50v1.5 and achieves lowest latency of all Mobilenet-V1 submissions (329μs). Ncore yields 23x speedup over other x86 vendor percore throughput, while freeing its own x86 cores for other work. Ncore is the only integrated solution among the memory intensive neural machine translation (NMT) submissions.
G. Glenn Henry, Parviz Palangpour, Michael Thomson, J. Scott Gardner, Bryce Arden, Jim Donahue, Kimble Houck, Jonathan Johnson, Kyle O'Brien, Scott Petersen, Benjamin Seroussi, Tyler Walker
ISCA8