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Nisarg Ujjainkar

dblp:270/8270 · DBLP profile ↗
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3ranked-venue papers
2as first author
2since 2021 · last 2024
0000-0001-6002-9583ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 58% Memory systems · 33% Energy-efficient computing · 9%
Computer graphics and multimedia
1 paper
Image and video coding · 87% Virtual and augmented reality · 13%

Topics — the 6 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Image and video coding › image compression
perceptual image compression
0.812024
Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality · ASPLOS (1) 2024
Image and video coding › image compression › perceptual image compression
perceptually lossless compression
0.812024
Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality · ASPLOS (1) 2024
Hardware accelerators and domain-specific architectures
image processing accelerator
0.712023
ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators · ISCA 2023
Hardware accelerators and domain-specific architectures › accelerator architecture
memory-efficient accelerator design
0.712023
ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators · ISCA 2023
Virtual and augmented reality › immersive display
virtual reality display
0.212024
Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality · ASPLOS (1) 2024
Energy-efficient computing › energy-efficient architecture
energy-efficient accelerator
0.212023
ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators · ISCA 2023

Methods — techniques the papers use, named apart from their topics

psychophysical study · 1.5color adjustment algorithm · 1.5
YearPublicationVenuePosition
2024 Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality
abstract
Virtual Reality (VR) has the potential of becoming the next ubiquitous computing platform. Continued progress in the burgeoning field of VR depends critically on an efficient computing substrate. In particular, DRAM access energy is known to contribute to a significant portion of system energy. Today's framebuffer compression system alleviates the DRAM traffic by using a numerically lossless compression algorithm. Being numerically lossless, however, is unnecessary to preserve perceptual quality for humans. This paper proposes a perceptually lossless, but numerically lossy, system to compress DRAM traffic. Our idea builds on top of long-established psychophysical studies that show that humans cannot discriminate colors that are close to each other. The discrimination ability becomes even weaker (i.e., more colors are perceptually indistinguishable) in our peripheral vision. Leveraging the color discrimination (in)ability, we propose an algorithm that adjusts pixel colors to minimize the bit encoding cost without introducing visible artifacts. The algorithm is coupled with lightweight architectural support that, in real-time, reduces the DRAM traffic by 66.9% and outperforms existing framebuffer compression mechanisms by up to 20.4%. Psychophysical studies on human participants show that our system introduce little to no perceptual fidelity degradation.
Nisarg Ujjainkar, Ethan Shahan, Kenneth Chen, Budmonde Duinkharjav, Qi Sun 0003, Yuhao Zhu 0001
ASPLOS (1)1
2023 ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators
abstract
Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm structures and/or on-chip memory resources. As a result, they either have narrow applicability or result in inefficient designs.
Nisarg Ujjainkar, Jingwen Leng, Yuhao Zhu 0001
ISCA1
2020 Prefetching in Hybrid Main Memory Systems
Subisha V, Varun Gohil, Nisarg Ujjainkar, Manu Awasthi
HotStorage3