Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a$64\times 64$array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.

The AI revolution shows the ever increasing performance demands of AI applications like Deep Neural Networks DNNs which consist of tens of layers and do computations on tens of millions of data weights [1]. Conventional Von Neumann architectures are currently struggling to meet these emerging performance demands with deep memory hierarchies to bridge the processor-memory performance gap [2]. Emerging technologies (like RRAMs) have meanwhile shown a real promise to address the increasing challenges of the conventional computing technology. While the main direction of research is focussing on exploiting the analogue memory attributes of RRAMs specially for analogue computing crossbars [3], this paper focuses on a different perspective of building high-density and digital-friendly RRAM-based memory that is a good alternative to the SRAM-based Last-Level Caches LLCs. This digital RRAM-based memory with conventional 1T1R bit-cells is proposed to be an on-chip gigantic data reservoir, with much higher density than SRAMs, to bridge the memory gap. The paper also shows that the digital RRAM-based memory is capable of doing robust bit-line compute which opens the door for digital in-memory computing architectures that can mitigate the Von Neumann bottleneck while adopting RRAM’s high-density promise. Unlike analogue RRAM crossbars, RRAMs’ digital in-memory computing capability should inherit the large scalability and the fast time-to-market of the digital domain with less engineering effort for optimisation as there is no need any more to build DACs and ADCs.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendly- associative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (≈4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 μW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

We design an Ion-Sensitive Field-Effect (ISFET) array leveraging on the two successful fields of neuromorphic electronics and chemical sensing to encode the signal in spikes and perform sensor processing between neighbouring pixels. The array is structured as clusters integrating 4 × 4 pixels with sensor compensation, taking advantage of spatial correlation of sensor non-idealities. The offset compensation is capable of calibrating in a range of 662 mV. The system shows a robust, scalable and power efficient architecture with a sensitivity ranging from 2.56 MHz/pH to 3.38 MHz/pH. The pixel occupies an area of 30μm × 24μm, and the cluster area is 205 μm × 205 μm. The layout of each pixel is spread out with digital blocks embedded in-between, which improves signal coupling by enlarging the chemical sensing area of each pixel. The system readout implements address event representation (AER) for triggering the outputs.