EDBT 2026 Demo / reviewers in the wild / expert
Steven Brzozowski
dblp:271/0541
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0002-5289-3184ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.6 | 1 | 2022 | Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems · IEEE Trans. Computers 2022 |
Memory systems › cache
cache behavior |
0.6 | 1 | 2022 | Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems · IEEE Trans. Computers 2022 |
Operating systems › extensible operating systems › kernel extensibility › kernel extensions
kernel module |
0.2 | 1 | 2022 | Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems · IEEE Trans. Computers 2022 |
Methods — techniques the papers use, named apart from their topics
snapshotting · 1.1cache introspection · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Observing the Invisible: Live Cache Inspection for High-Performance Embedded SystemsabstractThe vast majority of high-performance embedded systems implement multi-level CPU cache hierarchies. But the exact behavior of these CPU caches has historically been opaque to system designers. Absent expensive hardware debuggers, an understanding of cache makeup remains tenuous at best. This enduring opacity further obscures the complex interplay among applications and OS-level components, particularly as they compete for the allocation of cache resources. Notwithstanding the relegation of cache comprehension to proxies such as static cache analysis, performance counter-based profiling, and cache hierarchy simulations, the underpinnings of cache structure and evolution continue to elude software-centric solutions. In this article, we explore a novel method of studying cache contents and their evolution via snapshotting. Our method complements extant approaches for cache profiling to better formulate, validate, and refine hypotheses on the behavior of modern caches. We leverage cache introspection interfaces provided by vendors to perform live cache inspections without the need for external hardware. We present CacheFlow, a proof-of-concept Linux kernel module which snapshots cache contents on an NVIDIA Tegra TX1 system on chip and a Hardkernel Odroid XU4. Dharmesh Tarapore, Shahin Roozkhosh, Steven Brzozowski, Renato Mancuso 0001 |
IEEE Trans. Computers | 3 |