A generalized tracking loop is proposed for tracking MPSK signals at high SNR. It is similar in form to the polarity-type Costas loop used for tracking QPSK signals, in which limiters in the arms provide the data estimates needed for data wipeoff in forming the loop error signal. For the MPSK signal, the hard limiters are replaced by "multivalued limiters" withM/4 (M \geq 4)positive and negative values. The outputs of the multivalued limiters in each arm are theIandQprojections of the data. TheScurve is computed for this MPSK loop, and plotted for different SNR's. A comparison is made to theScurve for theMth power loop (orM-phase Costas loop), which is optimum for low SNR. From this comparison, a rough value of the "boundary" SNR can be obtained; this value may be used by the designer to determine which loop structure should be used. The advantage of the high SNR structure proposed here is that it is much simpler to implement than the corresponding low SNR structures.

The behavior of a digital phase-locked loop (DPLL) which tracks the positive-going zero crossings of the incoming signal can be characterized by a nonlinear difference equation in the phaseerror process. This equation was first presented by Gill and Gupta for the CW loop, and modified by Osborne and Lindsey for theNth power loop. Stability results have been previously obtained for first- and second-order loops by linearizing the equation about the steady-state solution. However, in this paper, a mathematically more rigorous and powerful approach is introduced whereby the acquisition behavior is studied by formulating the equation as a fixed-point problem. Stability results can be obtained by studying the nonlinear equation directly, using theorems pertaining to the convergence behavior of the Picard iterates, e.g., Ostrowski's Theorem and the Contraction Mapping Theorem. Using this formulation, we present some new stability results (and rederive some previously obtained results) for the first- and second-order DPLL's. Then, some stability results for the third-order DPLL are derived for the first time. The first-order DPLL results appear in Part I, and the higher order DPLL results appear in Part II.

The behavior of a digital phase-locked loop (DPLL) which tracks the positive-going zero crossings of the incoming signal can be characterized by a nonlinear difference equation in the phaseerror process. This equation was first presented by Gill and Gupta for the CW loop, and modified by Osborne and Lindsey for theNth power loop. Some stability results had been previously obtained by other authors for first- and second-order loops by linearizing the equation about the steady-state solution. In Part I, a mathematically more rigorous and powerful approach was introduced whereby the acquisition behavior was studied by formulating the equation as a fixedpoint problem. Stability results can be obtained by using theorems such as Ostrowski's Theorem and the Contraction Mapping Theorem. Part I then presented some new stability results (and rederived some previously obtained results) for first-order DPLL's. In Part II, we present the results for the second- and third-order DPLL's. It is shown how both second- and third-order DPLL's have gain-dependent limitations on the frequency offsets which can be withstood. These restrictions imply that the higher order DPLL's cannot track a frequency ramp, regardless of the ramp slope, and are in contrast to the results for analog loops. Important restrictions on the signal power are also noted for both loops.