Performance improvement of the nearly instantaneous companding PCM (or block companding PCM) is discussed. A simplified algorithm is proposed. The design and performance of a channel bank adopting the proposed algorithm is described. The channel bank can transmit 44 voiceband signals on a standard T1 line. It provides commercially acceptable speech quality as well as sufficient transparency for voiceband data up to 4800 bits/s.

The development of a microprocessor-controlled 96/48 DSI terminal is described. The terminal is intended for domestic use, and is designed so as to maximize compatibility with existing digital carrier systems, it merges four T1 signals into two T1 compatible bit streams for transmission. The terminal is given sufficient excess capacity to accommodate voiceband data, while retaining toll-grade transmission quality for speech. Implementation approaches and considerations in both calculated and measured system characteristics are described.

A discretely variable slope delta modulation (DVSD) codec is described, which is suitable for integrated circuit realization. The step size is varied by a pulse number modulation method that does not require a precision digital-to-analog conversion circuit. An adaptation algorithm is discussed, taking into consideration the effect of transmission errors. The quantizer and integrator portion has been fabricated on a monolithic chip using MOS technology. Results obtained from an experimental 32 kbit/s codec demonstrate its excellent performance.

A 120-channel transmultiplexer has been developed which interfaces two FDM basic supergroup signals (2 x 60 channels) directly to the digital time division switch or digital transmission systems. The equiplnent exploits a block processing digital SSB-FDM multiplex/demultiplex scheme, and has been built using newly developed high-speed CMOS pipeline multipliers and variable length shift registers. System design considerations and hardware implementation techniques are described in detail as well as the measured performance.

A new method for digital implementation of SSB-FDM modulation and demodulation is presented, which utilizes the FFT algorithm to reduce the multiplication rate. The hardware realization of the presented method is shown to be the simplest; it consists of only an FFT processor and a set of complex bandpass filters which operate at the same rate as the input baseband sequences; no signal conversions are required prior to FFT processing. Simple and practical approaches are presented for design and implementation of the EFT processor and the set of complex bandpass filters. Design examples, which are made for implementation of a TDM-FDM translator at the supergroup level, show that the proposed method can attain the minimum multiplication rate among methods previously reported.